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作者(中文):蔡宗霖
作者(外文):Tsai, Tsung-Lin
論文名稱(中文):針對極化碼適合硬體實作之促進型置信傳播解碼方法
論文名稱(外文):A Hardware-Friendly Expediting Belief Propagation Decoding for Polar Codes
指導教授(中文):翁詠祿
指導教授(外文):Ueng,Yeong-Luh
口試委員(中文):李晃昌
王忠炫
學位類別:碩士
校院名稱:國立清華大學
系所名稱:通訊工程研究所
學號:103064520
出版年(民國):106
畢業學年度:105
語文別:英文
論文頁數:55
中文關鍵詞:極化碼置信度傳播解碼和積演算法疊代解碼器最小和演算法
外文關鍵詞:Polar CodesBelief Propagation (BP) DecodingSum-Product Algorithmiterative decoderMin-Sum Algorithm
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對於現行針對極化碼(Polar Code)的置信傳播解碼(belief propagation decoding,BP decoding)仍然需要使用大量的疊代來完成,所以解碼器的的吞吐量(throughput)也因此受到侷限。在本文中,我們提出一個適合硬體實作之改善置信傳播效率的增強技術(expediting technology,Ex-)來提升其解碼的收斂速度並保持錯誤率表現,這項技術主要藉由在疊代時增強可靠的對數相似度比率(log-likelihood ratio,LLR)值來加速解碼收斂。在幾乎沒有錯誤率損失的情形下,此項技術能夠減少接近一半的解碼疊代次數,而針對這項技術,我們也提出了一個低複雜度的流程來幫助我們決定所需要的參數。在硬體實現上,這個增強技術可以有效的減少解碼疊代的延遲並且顯著的提升吞吐量。最後,我們使用台積電90奈米製成來實作這項增強技術在雙向傳播架構上,此技術提升了了20.1%的吞吐量同時改善了14.82%的硬體面積使用效率。
It is known that the conventional belief propagation (BP) decoding for polar codes requires a large number of iterations, and, hence, the decoder throughput is limited. In this thesis, we propose a hardware-friendly method, called "expediting technology (Ex-)", to improve the convergence speed in error-rate performance. The main idea is to strengthen the reliable log-likelihood ratio (LLR) value during iterations to expedite convergence. This technique is believed to reduce nearly half of iterations almost without performance reduction. Next, we introduce a low-complexity method for selecting parameters of expediting technology. In hardware implementation, the expediting technology significantly reduces decoding latency and clearly improves throughput. Finally, we implemented proposal on bidirectional-propagation architecture in TSMC 90nm COMS process. This technique improves throughput by 20.1% in compare with bidirectional-propagation architecture, which improves area efficiency (TAR) by about 14.82%.
Abstract . . . . . . . . . . . . . . . . . . .I
中文摘要 . . . . . . . . . . . . . . . . . . II
第一章簡介 . . . . . . . . . . . . . . . . . .1
第二章極化碼邊解碼的回顧 . . . . . . . . . . .5
第三章適合硬體實作之解碼次數減少的方法 . . . 11
第四章硬體實作與測試結果 . . . . . . . . . . 35
第五章結論 . . . . . . . . . . . . . . . . . 45
第六章附錄 . . . . . . . . . . . . . . . . . 46
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