近年來，消費性電子產品如智慧型手機、穿戴式裝置、平板電腦等的普及以及消費者對於裝置多功能的需求，隨著科技的發展記憶體容量的提升以及更快的存取速度。記憶體可簡單的被歸類為揮發性(Volatile)以及非揮發性(Non-volatile)，揮發性記憶體有著極快的寫入以及讀取速度優勢，然而面積大以及物理限制使得此種記憶體很難隨著製程發展微縮，非揮發性記憶體中快閃記憶體(Flash memory)主宰非揮發性記憶體市場，但是高操作電壓以及微縮困難，使得新型記憶體得以加速發展，其中電阻式記憶體有著極高的潛力成為下一世代記憶體主流。嵌入式電阻記憶體(Embedded RRAM)中有著極佳的相容性，能夠相容於28奈米之前所有製程，然而隨著製程發展從2D結構進入3D鰭式電晶體，Embedded RRAM勢必需要改良才有辦法在先進製程中實現。
在本論文之中，成功地展示與驗證一完全相容於16 nm互補式金氧半(CMOS)邏輯製程技術下之新穎的接觸電阻式記憶體(FIND RRAM) 相容於先進鰭式場效電晶體邏輯製程。此種新電阻式記憶體不用增加額外光罩或特殊製程步驟，並且記憶元面積288 nm x 265 nm，具有相當高競爭力。藉由電性分析，此電阻式記憶體操作電壓低和快速轉態的特性，並且在可靠度方面設置/重置干擾測試、連續讀取測試顯示出優秀的特性。為了瞭解FIND RRAM的電阻轉換機制，利用起因於電子捕捉與釋放產生的隨機電報雜訊(RTN)之量測法，進一步探討FIND RRAM堆疊層之特性。由RTN模型的輔助之下，量測而得的資料可被用於參數的萃取與分析，以致最終發展出一陷阱引發電阻切換之預測模型。

Recently , due to the rapidly developing of commercial electronics, the demands of fast and mass storage devices increase. The mainstream NVM that dominate the market nowadays, Flash, have suffered from a spectrum of challenges--current leakage, ultra-high apply voltage, and, most important, scale possibility. These barrier, paradoxically, serve as catalyst for full-bloom investigation on new memory technology, especially resistive random access memory, RRAM.As the CMOS process is reaching a limit with the planar structure, FinFET is needed to maintain the scalability and performance of logic integrated circuits.In this dissertation, we propose a embedded RRAM structure that is fabricated by advanced 16nm FinFET CMOS logic process. This memory cell is fully compatible with CMOS logic process without any extra process flow or mask. The new FIND RRAM exhibits a very low set voltage and reset current resulting from the field enhancement on fin corners. The set/reset disturb test, continuous read test , endurance and no reliability concern which guarantee this memory cell as the candidate for next generation.
The random telegraph noise (RTN) generated by electron trapping/de-trapping on the stacking layers was also investigated to determine the RRAM switching mechanism. The RTN model makes it possible for parameter extraction from the measured data. Analyzing the extracted parameters and the measured results lead to a proposed trap-induced resistive switching model.

摘要 I
ABSTRACT III
致謝 IV
內文目錄 VI
附圖目錄 IX
附表目錄 XIV
第一章 1
1.1 前言 1
1.2 論文大綱 3
第2章 電阻式隨機存取記憶體技術與其應用 4
2.1 電阻式隨機存取記憶介紹 4
2.1.1 文獻回顧 4
2.1.2 初始化操作及特性分布 5
2.1.3 操作與極性特性 7
2.2 電阻式記憶體模型 8
2.2.1 自我加速熱溶解模型 8
2.2.2 氧空缺粒子跳躍模型 10
2.3 電阻式記憶體陣列驅動相關研究 11
2.3.1 交叉點電阻式記憶體 11
2.3.2 二極體驅動之電阻式記憶體 12
2.3.3 金氧半電晶體驅動之電阻式記憶體 13
2.4 小結 13
第3章 FINFET電阻式隨機存取記憶體 26
3.1 FINFET電阻式隨機存取記憶體 26
3.1.1 元件結構 27
3.1.2 量測環境介紹 28
3.2 元件電性操作及結構對電性之影響 29
3.3 小結 31
第4章 操作最佳化及可靠度分析 45
4.1 元件操作之測試及最佳化 45
4.2 可靠度分析 47
4.3 小結 49
第5章 利用隨機電報雜訊分析FIND RRAM之電阻轉換模型 66
5.1 隨機電報亂數雜訊介紹及分析 66
5.2 隨機電報雜訊模型 69
5.3 陷阱引發電阻轉換模型 71
5.4 小結 73
第6章 總結 90
參考文獻 91

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