隨著半導體最小線寬縮小到奈米尺度的今日，場效電晶體的源極和汲極越來越接近，使得閥極沒有辦法完全控制通道開關，導致即使是在閥極接地的情況下也有顯著的漏電流產生。為了解決電晶體的漏電問題，科學家們提出了鰭式電晶體(FinFET)結構來增強通道的控制能力，然而FinFET的三維結構卻帶來了多餘且顯著的寄生電阻電容，這些都會對電路造成很大的影響。為了瞭解寄生電阻電容造成影響的主要因素，我們採用非對稱的FinFET模型去模擬分析。模擬結果顯示寄生電阻與電容會在源極和汲極兩端產生不同程度的影響。藉由這個結果，我們仔細研究了FinFET佈局並提出了兩種方法去減少寄生電阻對電路的影響。一個是把源極和汲極的VIA0移到中間，另一個則是增加兩極VIA0的數量，兩種方式都經過實際下線驗證成功。此外，我們也研究了非對稱FinFET佈局面積與電路效能之間的關係，不過由於佈局規定上的限制，並沒有下線做更進一步驗證與分析。

As the feature size of the semiconductor technology shrunk to nanometer scale, the distance between source and drain of a MOSFET becomes so short such that the gate lose full control of the channel, and thus there is significant leakage current even when gate is grounded. FinFET technology has been adopted to solve this leakage problem. However, FinFET’s 3D structure incorporates significant parasitic capacitance and resistance and that can have larger impacts on circuit performance. To study the dominating factor of the impacts, asymmetric FinFET transistors have been constructed and simulated extensively. It confirms that parasitic resistance and capacitance contribute differently for the source drain terminals. Using this information, the FinFET gate layout is reviewed and two approaches to reduce the parasitic resistance impacts are proposed. One is move the VIA0 position to the center and the other is to increase the number of VIA0. Both approaches were verified by silicon test chips. Asymmetric FinFET transistor layouts that can trade off performance and area have also been developed. However, due to design rule constraints these layouts have not been verified.

摘要 I
Abstract II
誌謝 III
Table of Content V
List of Figures VII
List of Tables X
Chapter 1 Introduction 1
1.1 Background and Motivation 1
1.2 Thesis Organization 2
Chapter 2 Parasitic Resistance and Capacitance Impacts on FinFET Gates 3
2.1 Simulation Setup 3
2.2 Source and drain resistance 4
2.2.1 DC Analysis 4
2.2.2 Transient Analysis 7
2.2.2.1 Inverter Chain 7
2.2.2.2 ND2 Gate 9
2.2.2.3 Pass and Transmission Gates 14
2.3 Parasitic Capacitance 19
2.3.1 Transient Analysis 19
2.3.1.1 INV 20
2.3.1.2 ND2 Gate 20
2.4 Summary 27
Chapter 3 FinFET Layout and Parasitic RC 28
3.1 FinFET Structures and Layouts 28
3.1.1 FinFET layout 29
3.1.2 Layout constraints 30
3.2 Parasitic Capacitance 31
3.2.1 Larger fingers Layout 32
3.2.1.1 INV 33
3.2.1.2 NAND2 gate 39
3.3 FinFET source /drain parasitic resistor model 43
3.3.1 Impacts of VIA0 location 43
3.3.2 Impacts of VIA0 number 45
3.3.3 Impacts on larger fins structure 46
3.3.4 Current sensitivity of S/D parasitic resistance 47
3.3.5 Impacts on circuit performance 50
3.4 Summary 53
Chapter 4 Layout Modification and Silicon verification 55
4.1 Proposed layout Modification 55
4.1.1 Parasitic capacitance 56
4.2 Test line design 57
4.2.1 Ring oscillator 57
4.2.2 Multiple finger layouts 59
4.3 Silicon measurements 60
4.3.1 Ring oscillator 60
4.3.2 One finger and multiple fingers transistors 64
4.3.2.1 Single transistor 64
4.3.2.1 Inverter 71
4.4 Summary 73
Chapter 5 Conclusions and Future work 75
5.1 Conclusions 75
5.2 Future work 76
Reference 78

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