本篇論文討論閘極介電層的可靠度問題，分成兩個主題，時依性介電層崩潰(TDDB)以及負偏壓溫度不穩定性(NBTI)。
時依性介電層崩潰(TDDB)以N型鰭式電晶體探討，針對氧化層內陷阱討論介電層的退化與崩潰特性，經由量測閘極的應力導致漏電流(SILC)的結果，N型鰭式電晶體的應力導致漏電流增長為30%，相較於以往平面電晶體應力導致漏電流為300%，因此先進的電晶體對於SILC有相當程度的改善。以崩潰模型對介電層的崩潰進行分析，發現熱化學以及陽極電洞注入模型在N型鰭式電晶體中趨勢符合，以熱化學模型萃取相關的電壓加速因數(voltage acceleration factor) 為6(1/V)，而十年壽命的安全操作電壓將小於1.6V。
負偏壓溫度不穩定性(NBTI)以P型鰭式電晶體探討，針對介面層陷阱討論元件的退化，經過1000秒加壓的正反掃下，因為屬於垂直型施加應力，發現正反掃狀態下的退化差距並不大，且可以發現臨界電壓的變化和時間 成正比，n為0.2~0.3。

This thesis presents the studies of the gate dielectric reliabilities in FinFETs. Two topics are covered in this thesis: time dependent dielectric breakdown (TDDB) and negative bias temperature instability (NBTI).
The TDDB of N type FinFETs were measured and the oxide trap densities were studied. The gate stress induced leakage currents (SILC) for N-FinFETs are found to be increased by 30% over the fresh devices. As compare to the reported 300% increase in SILC for planar MOSFET, an order of magnitude reduction in the increase of SILC is observed. Thus, FinFETs has a better gate SILC than planar MOSFET. Thermochemical and anode hole injection model are used to study the dielectric breakdown. It appears that both models seem to fit the measured data reasonably good for N-FinFETs. With the use of the thermochemical model, voltage acceleration factor  is 6(1/V) and 10 year life-time safety operation voltage shall be under about 1.6V.
The NBTI for P type FinFETs is studied along with its interface trap density. After 1000s forward and reverse sweep, the difference in degradation between forward and reverse sweep is small. Moreover, threshold voltage shift has power law dependence ( ) and n=0.2~0.3.

致謝 II
中文摘要 III
英文摘要 IV
圖目錄 VII
表目錄 IX
第一章 緒論
1.1 金氧半場效電晶體的微縮與挑戰 1
1.2 鰭式電晶體閘極氧化層可靠度問題 2
1.3 論文架構 5
第二章 文獻回顧
2.1 鰭式電晶體v.s平面電晶體 13
2.2 時依性介電層崩潰機制 14
2.2.1 應力導致漏電流 14
2.2.2 氧化層的崩潰現象 15
2.3 介電層崩潰之物理模型 17
2.3.1 熱化學模型 18
2.3.2 陽極電洞注入模型 19
2.4 負偏壓溫度不穩定性 21
2.4.1 反應-擴散模型 21
第三章 量測方法
3.1 樣品量測與機台介紹 34
3.2 量測方法 35
3.2.1 斜坡式電壓加壓 35
3.2.2 固定電壓加壓 35
3.2.3 S-M-S 方法 35
第四章 結果與討論
4.1 閘極氧化層的退化 39
4.1.1 不同電壓下的應力導致漏 39
4.1.2 不同溫度下的應力導致漏電流 40
4.2 軟崩潰與硬崩潰的量測 41
4.3 元件壽命的預測 43
4.4 負偏壓溫度不穩定性的量測 46
第五章 結論與未來展望
5.1 結論 60
參考文獻

[1]http://www.techdesignforums.com/blog/2014/04/07/itrs-m1-half-pitch-node-scaling-slowdown/ [online]
[2] W.-C. Lee and C. Hu, “Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling,” IEEE Trans. Electron Devices, vol. 48, pp. 1366–1373, July 2001
[3] J. C. Ranuarez, M. J. Deen, and C.-H. Chen, “A review of gate tunneling current in MOS device,” Microelectron. Reliab., available online, 2006.
[4] F. Crupi, R. Degraeve, A. Kerber, D. H. Kwak, and G. Groeseneken, “Correlation between stress-induced leakage current (SILC) and the HfO2 bulk trap density in a SiO2/HfO2 stack,” in Int. Reliab. Phys. Symp., 2003, pp. 181–187.
[5] J. Wu, L. Register, and E. Rosembaum, “Trap-assisted tunneling current through ultra-thin oxide,” in Proc. IRPS Symp., 1999, p. 389
[6] S. Kamohara, D. Park, and C. Hu, “Deep-trap SILC (Stress-Induced Leakage Current) model for nominal and weak oxides,” in Proc. IRPS, 1998, pp. 57–61.
[7] https://nanohub.org/resources/16560 [online]
[8] T. Pompl, C. Engel, H. Wurzer, and M. Kerber, “Soft breakdown and hard breakdown in ultrathin oxides,” Microelectron. Reliab., vol. 41, pp. 543–551, Apr. 2001.
[9] J. S. Suehle, B. Zhu, Y. Chen, and J. B. Bernstein, “Detailed study and projection of hard breakdown evolution in ultra-thin gate oxides,” Microelectron. Reliab., vol. 45, no. 3–5, pp. 419–426, Feb. 2005.
[10] S. Sahhaf, R. Degraeve, P. Roussel, B. Kaczer, T. Kauerauf, and G. Groeseneken, “A new TDDB reliability prediction methodology accounting for multiple SBD and wear out,” IEEE Trans. Electron Devices, vol. 56, no. 7, pp. 1424-1432, 2009.
[11] E. Y. Wu et al., “Power-law voltage acceleration: A key element for ultra-thin gate oxide reliability,” Microelectron. Rel., vol. 45, no. 12, pp. 1809–1834, 2005.
[12] J. W. McPherson, “Time dependent dielectric breakdown physics— Models revisited,” Microelectron. Rel., vol. 52, nos. 9–10, pp. 1753–1760, Sep./Oct. 2012.
[13] http://www.ora.nsysu.edu.tw/jl/123.htm [online]
[14] G. Bersuker, D. Heh, C. Young, H. Park, P. Khanal, L. Larcher, A. Padovani, P. Lenahan, J. Ryan, B. H. Lee, H. Tseng, and R. Jammy, “Breakdown in the metal/high-k gate stack: Identifying “weak link” in the multilayer dielectric,” in IEDM Tech. Dig., 2008, pp. 791–794
[15] A. Neugroschel, G. Bersuker, R. Choi, C. Cochrane, P. Lenahan, D. Heh, C. Young, C. Y. Kang, B. H. Lee, and R. Jammy, “An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO2 gate stacks,” in IEDM Tech. Dig., 2006, pp. 1–4
[16] Stathis, J.H; and S. Zafar, “The negative bias temperature instability in MOS devices: A review,” Microelectronics Reliability, Vol.46, No.2-4, 2006.
[17] S. Lombardo, J. H. Stathis, B. P. Linder, K. L. Pey, F. Palumbo, and C. H. Tung, “Dielectric breakdown mechanisms in gate oxides,” J. Appl. Phys., vol. 98, no. 12, p. 121 301, Dec. 2005
[18] X. Li, J. Qin, and J. B. Bernstein, “Compact modeling of MOSFET wearout mechanisms for circuit-reliability simulation,” IEEE Trans. Device Mater. Rel., vol. 8, no. 1, pp. 98–121, Mar. 2008
[19] P. E. Nicollian, W. R. Hunter, and J. C. Hu, “Experimental evidence for voltage driven breakdown models in ultrathin gate oxides,” in Proc. 2000 Int. Reliability Physics Symp., 2000, pp. 7–15.
[20] G. Ribes, S. Bruyere, F. Monsieur, D. Roy, and V. Huard, “New insights into the change of voltage acceleration and temperature activation of oxide breakdown,” Microelectron. Reliab., vol. 43, no. 8, pp. 1211–1214, Aug. 2003.
[21] K. Kobayashi, A. Teramoto, and H. Miyoshi, “Origin of positive charge generated thin SiO during high-field electrical stress,” IEEE Trans. Electron Devices, vol. 46, pp. 947–953, May 1999
[22] J. W. McPherson, R. B. Khamankar, and A. Shanware, “Complementary model for intrinsic time dependent dielectric breakdown in SiO dielectrics,” J. Appl. Phys., vol. 8, pp. 5351–5359, 2000.
[23] Q. Jin and J. B. Bernstein, “Non-Arrhenius temperature acceleration and stress-dependent voltage acceleration for semiconductor device involving multiple failure mechanisms,” in Proc. IEEE Int. Integrated Rel. Workshop, South Lake Tahoe, CA, USA, Oct. 16–19, 2006, pp. 93–97.
[24] T. Kauerauf et al., “Methodologies for Sub-1nm EOT TDDB Evaluation,” in Proc. Int. Rel. Phys. Symp., 2011, pp. 7-16.
[25] M. Jurczak, N. Collaert, A. Veloso, T. Hoffmann, and S. Biesemans, “Review of FinFET technology,” in Proc. IEEE Int. SOI Conf., Oct. 2009, pp. 1–4.