對於相同容量來說，動態隨機存取記憶體比起靜態隨機存取記憶體面積會比較小，因此成本效益會比較高；而比起快閃記憶體，動態隨機存取記憶體的速度又比較快，因此嵌入式動態隨機存取記憶體被廣泛應用在多數的電子產品中。
不過在中央處理器中，普遍使用靜態隨機存取記憶體來當作快取記憶體，因為靜態隨機存取記憶體本身讀取的速度較快。但是對於資料量需求日益龐大的現在，使用靜態隨機存取記憶體來當作快取記憶體使容量逐漸不足。
為了改善這個情形，我們使用動態隨機存取記憶體來當作快取記憶體，因為靜態隨機存取記憶體由六個電晶體組成，但動態隨機存取記憶體只需要一個電晶體及一個電容，因此可以大大的節省面積，達到大容量的目的。
我們也設計了一個新型的三元循址比較電路，和動態隨機存取記憶體結合之後，在中央處理器比較標籤的過程中，可以同時達到大容量和省電的效果。
我們使用台積65奈米標準CMOS的製程，在一個4Kb的內嵌式動態隨機存取記憶體晶片來實現此提案。

For same capacity, dynamic random access memory (DRAM) has smaller area than static random access memory (SRAM). So it’s more cost-effective than SRAM. And compared to FLASH, DRAM’s speed is higher. That’s why DRAM is widely used in many electronics products.
But in CPU, usually we use SRAMs as cache due to its high speed. But nowadays, the demand for high quantity data becomes more and more urgent. So using SRAM as cache is insufficient for capacity.
To improve this situation, we replace SRAM with DRAM as cache. Because SRAM is composed of six transistors but DRAM only has one transistor and one capacitor. DRAM will effectively save area and achieve the goal of high capacity.
We also designed an innovative TCAM circuit and combined with eDRAM. In the process of CPU finding tags, we can achieve the effect of high capacity and low power at the same time.
We use TSMC 65nm generic CMOS process and realize this proposal in a 4Kb eDRAM memory macro. We have detailed circuit analysis and measurement result in the following article.

致謝 iii
Contents iv
List of Figures vi
List of Tables viii
Chapter 1 eDRAM Description 1
1.1 eDRAM Structure 1
1.2 Leakage Mechanisms 3
1.2.1 Sub-threshold Leakage (I1) 4
1.2.2 Gate-Induced Drain Leakage (I2) 5
1.2.3 Gate-Oxide Tunneling Current (I3) 6
1.2.4 Hot Carrier Injection Current (I4) 7
1.2.5 Reversed Biased Junction BTBT Leakage (I5) 8
1.2.6 Punch Through Current (I6) 9
1.3 Write Operation 10
1.4 Read Operation 12
1.5 Refresh Operation 13
1.6 eDRAM Application 15
Chapter 2 TCAM Description 15
2.1 Introduction of CAM 15
2.2 Introduction of TCAM 18
2.3 TCAM Macro 19
Chapter 3 Proposed Scheme 19
3.1 Motivation 19
3.2 Proposed Circuit & Operating Scheme Evolution 22
3.2.1 Proposed Circuit 22
3.2.2 Operating Scheme: SA Push-Pull Method 23
3.2.3 Operating Scheme: Q-Share Method 25
3.2.4 Operating Scheme: VSS Driving Method 28
3.3 Analysis of Proposed Circuit and Other Work 31
Chapter 4 Macro Implementation 37
4.1 eDRAM Macro 37
4.1.1 eDRAM Cell Array 38
4.1.2 Peripheral Circuits 39
4.2 Design of Testchip 39
Chapter 5 Measurement Results and Conclusion 41
5.1 Measurement Results 42
5.2 Conclusion and Future Work 44
Reference 46

[1] E. Gerritsen, et al., "Evolution of materials technology for stacked-capacitors in 65 nm embedded-DRAM," Solid-State Eletronics, vol. 14, pp. 1767-1775, 2005.
[2] H. Takato, "Embedded DRAM Technologies," Solid-State Device Research Conference, pp. 13-18, 2000.
[3] H. Ishiuchi, et al., "Embedded DRAM technologies," International Electron Devices Meeting Technical Digest, pp. 33-36, 1997.
[4] H. Takato, "Embedded DRAM Technologies," Solid-State Device Research Conference, pp. 13-18, 2000.
[5] K. Itoh, et al., "VLSI memory technology: Current status and future trends," Solid-State Circuits Conference, pp. 3-10, 1999.
[6] P. W. Diodato, "Embedded DRAM: more than just a memory," Communications Magazine, vol. 38, pp. 118-126, 2000.
[7] A. Wang, et al., " Design of ultra-low-power smart wearable systems," Latin-American Test Symposium (LATS), pp. 1-2, 2015.
[8] K. Itoh, "VLSI Memory Chip Design," Springer, 2001.
[9] K. Itoh, et al., "Ultra-Low Voltage Nano-Scale Memories," Springer, 2007.
[10] B. L. Anderson, et al., "Fundamentals of Semiconductor Devices," McGraw-Hill, 2005.
[11] K. Roy, et al., "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits," Proceedings of the IEEE, vol. 91, pp. 305-327, 2003.
[12] H. Falk, "Prolog to: Leakage current mechanisms and leakage reduction techniques in deep-submicrometer cmos circuits," Proceedings of the IEEE, vol. 91, pp. 303-304, 2003.
[13] S. Mukhopadhyay, et al., "Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, pp. 1486-1495, 2006.
[14] K. Zhang, Embedded Memories for Nano-Scale VLSIs: Springer, 2009.
[15] Y. Taito, et al., "A high density memory for SoC with a 143MHz SRAM interface using sense-synchronized-read/write," IEEE International Solid-State Circuits Conference Digest of Technical Papers, vol.1, pp.306-307, 2003.
[16] J. Y. Sim, et al., "A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor," IEEE Journal of Solid-State Circuits, vol. 38, pp. 631-640, 2003.
[17] A. Valero, et al., "An hybrid eDRAM/SRAM macrocell to implement first-level data caches," the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, 2009.
[18] S. Tomishima, et al., "A 1.0-V 230-MHz Column Access Embedded DRAM for Portable MPEG Applications," IEEE Journal of Solid-State Circuits, vol. 36, pp. 1728-1737, 2001.
[19] S. Tomishima, et al., "A 1.0 V 230 MHz column-access embedded DRAM macro for portable MPEG applications," IEEE International Solid-State Circuits Conference, pp. 384-385, 2001.
[20] K. Pagiamtzis, et al., "Content-addressable memory (CAM) circuits and architectures: a tutorial and survey," IEEE Journal of Solid-State Circuits, vol. 41, pp. 712-727, 2006.
[21] A. Kumar, et al., "Power and performance efficient secondary cache using tag bloom architecture," Electronics and Communication Systems, pp. 1-5, 2014.
[22] P. Reviriego, et al., "FastTag: A Technique to Protect Cache Tags Against Soft Errors," IEEE Transactions on Device and Materials Reliability, vol. 14 pp. 935-937, 2014.
[23] S. Liu, et al., "Achieving non-polluting cache accessing by using data valid tag splitting," Computer Science and Network Technology, pp. 477-481, 2012.
[24] S. Wang, et al., "Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays," Transactions on Very Large Scale Integration, vol. 20, pp. 643-654, 2012.
[25] J. Lee, et al., "TLB index-based tagging for cache energy reduction," Low Power Electronics and Design, pp. 85-90, 2011.
[26] G. Theodorou, et al., "A software-based self-test methodology for in-system testing of processor cache tag arrays," International On-Line Testing Symposium, pp. 159-164, 2010.
[27] M. Zhang, et al., "Reducing cache energy consumption by tag encoding in embedded processors," Low Power Electronics and Design, pp. 367-370, 2007.
[28] J. Valls, et al., "The Tag Filter Cache: An Energy-Efficient Approach," Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, pp. 182-189, 2015.
[29] V. Hamacher, et al., "Computer Organization," McGraw Hill, pp. 224-238, 1996.
[30] M. Blash, et al., "Computer Architecture," Adison-Wesley Publishing Company, pp. 273-280, 1990.