於1980年代，半導體晶片最主要的可靠度問題是由熱載子所造成，而透過「幸運電子模型」，可以完美描述熱載子的行為。然而，以幸運電子模型中的描述，短通道元件操作在低電壓下，熱載子不再是可靠度上重要的問題。在本論文中，研究了N型短通道鰭式電晶體在低於1.5伏特下的熱載子退化現象。
　　從實驗的數據中，我們發現N型鰭式短通道場效電晶體在1.5伏特以下的操作，仍然造成熱載子退化，有些現象與在傳統平面長通道下的熱載子退化現象相同，如在反掃IDVG下的各項表現都比較差，缺陷都集中在汲極。不管是臨界電壓或是驅動電流的退化的時間指數皆大於0.3。反之，有些現象卻大不相同，如當閘極電壓與汲極電壓相同時，甚至大於汲極電壓時，會產生最大的基底電流。高溫下元件有較嚴重熱載子退化趨勢。驅動電流退化的時間指數與閘極電壓沒有相依性。另外，透過隨機電報雜訊的量測手法分析熱載子退化，隨著退化的發生，電報雜訊也會產生變化。主要觀察到的缺陷在二氧化矽內，觀察到的缺陷垂直深度，隨熱載子的退化並沒有太大改變。

　　In 1980, hot carrier instability (HCI) is the main problem of reliability in semiconductor industry. With the proposition of the Lucky Electron Model (LEM), the behavior of HC was well explained. However, based on LEM we expect that HCI will be unimportant for devices with low operating voltage. In this thesis, hot carrier effects on VDD less than 1.5V devices were studied.
　　From experiments, it is clear that HCI prevails for short channel N-FinFET with operating below 1.5V. Some observations are consistent with long channel planar MOSFETs. Such as, VTH and SS are worse in reverse IDVG sweep, which means the induced traps mostly located on the drain side. The time exponents of hot carrier degradation are higher than 0.3. However, there some observations are completely different. The bias conditions of maximum substrate current shift from VG=0.5VD to VG=VD even VG>VD. Devices degrade more severe in higher temperature.

致謝 i
摘要 ii
Abstract iii
內文目錄 iv
附圖目錄 vi
1 第一章一 序論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文大綱 3
2 第二章二 文獻回顧 4
2.1 摩爾定律與電晶體微縮之路 4
2.1.1 應變矽簡介 5
2.1.2 高介電係數介電層/金屬閘極簡介 7
2.1.3 三維結構電晶體簡介 8
2.2 幸運電子模型(Lucky Electron Model) 12
3 第三章三 熱載子退化之電性分析實驗 16
3.1 量測儀器與流程介紹 16
3.2 魚鰭式場效電晶體 19
3.2.1 結構簡介 19
3.2.2 電性量測分析 21
3.3 偏壓條件與電性分析 25
3.3.1 臨界電壓(Threshold Voltage)定義 25
3.3.2 次臨界擺幅(Sub-Threshold Swing)定義 26
3.4 數據分析 28
3.4.1 基底電流萃取 28
3.4.2 基本熱載子退化分析 33
3.4.3 正反掃退化分析 37
3.4.4 不同溫度退化分析 39
3.4.5 不同閘極電壓退化分析 41
3.4.6 不同汲極電壓退化分析 44
4 第四章四 利用隨機電報雜訊分析熱載子退化實驗 46
4.1 簡介 46
4.1.1 橫向陷阱分佈分析 50
4.1.2 縱向陷阱深度分析 51
4.1.3 實驗流程 53
4.2 數據分析 55
5 第五章五 總結 60
5.1 結論 60
5.2 未來展望 60
參考文獻 61

[1] R. Thewes, M. Brox, K. F. Goser, and W. Weber, "Hot-carrier degradation of p-MOSFET's under analog operation," IEEE Transactions on Electron Devices, vol. 44, pp. 607-617, 1997.
[2] J.-T. Park, B.-J. Lee, D.-W. Kim, C.-G. Yu, and H.-K. Yu, "RF performance degradation in nMOS transistors due to hot carrier effects," IEEE Transactions on Electron Devices, vol. 47, pp. 1068-1072, 2000.
[3] J. Pimbley and G. Gildenblat, "Effect of hot-electron stress on low frequency MOSFET noise," IEEE Electron Device Lett, vol. 5, pp. 345-347, 1984.
[4] E. Takeda, C. Y.-W. Yang, and A. Miura-Hamada, Hot-carrier effects in MOS devices: Academic Press, 1995.
[5] J. Hoyt, H. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, et al., "Strained silicon MOSFET technology," in Electron Devices Meeting, 2002. IEDM'02. International, 2002, pp. 23-26.
[6] M. L. Lee and E. A. Fitzgerald, "Hole mobility enhancements in nanometer-scale strained-silicon heterostructures grown on Ge-rich relaxed Si1− xGex," Journal of applied physics, vol. 94, pp. 2590-2596, 2003.
[7] K. Rim, J. Chu, H. Chen, K. Jenkins, T. Kanarsky, K. Lee, et al., "Characteristics and device design of sub-100 nm strained Si N-and PMOSFETs," in VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on, 2002, pp. 98-99.
[8] S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, et al., "A logic nanotechnology featuring strained-silicon," IEEE Electron Device Lett, vol. 25, pp. 191-193, 2004.
[9] A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, et al., "Local mechanical-stress control (LMC): A new technique for CMOS-performance enhancement," in Electron Devices Meeting, 2001. IEDM'01. Technical Digest. International, 2001, pp. 19.4. 1-19.4. 4.
[10] C. Gallon, G. Reimbold, G. Ghibaudo, R. Bianchi, and R. Gwoziecki, "Electrical analysis of external mechanical stress effects in short channel MOSFETs on (001) silicon," Solid-State Electronics, vol. 48, pp. 561-566, 2004.
[11] Y. Wang, D. Scott, J. Wu, J. Waller, J. Hu, K. Liu, et al., "Effects of uniaxial mechanical stress on drive current of 0.13 μm MOSFETs," IEEE Transactions on Electron Devices, vol. 50, pp. 529-531, 2003.
[12] "Intel's High k/Metal Gate Announcement," 2003.
[13] S. Toyoda, J. Okabayashi, H. Kumigashira, M. Oshima, K. Yamashita, M. Niwa, et al., "Crystallization in HfO2 gate insulators with in situ annealing studied by valence-band photoemission and x-ray absorption spectroscopy," Journal of applied physics, vol. 97, pp. 104507-104507, 2005.
[14] R. Puthenkovilakam, M. Sawkar, and J. P. Chang, "Electrical characteristics of postdeposition annealed HfO2 on silicon," Appl. Phys. Lett., vol. 86, p. 2902, 2005.
[15] J. Park, M. Cho, S. K. Kim, T. J. Park, S. W. Lee, S. H. Hong, et al., "Influence of the oxygen concentration of atomic-layer-deposited HfO2 films on the dielectric property and interface trap density," Appl. Phys. Lett., vol. 86, 2005.
[16] J. Robertson, O. Sharia, and A. Demkov, "Fermi level pinning by defects in HfO2-metal gate stacks," Appl. Phys. Lett., vol. 91, pp. 132912-132912, 2007.
[17] K. Akiyama, W. Wang, W. Mizubayashi, M. Ikeda, H. Ota, T. Nabatame, et al., "V FB Roll-off in HfO 2 Gate Stack after High Temperature Annealing Process-A Crucial Role of Out-diffused Oxygen from HfO 2 to Si," in 2007 IEEE Symposium on VLSI Technology 2007, pp. 72-73.
[18] M. V. Fischetti, D. A. Neumayer, and E. A. Cartier, "Effective electron mobility in Si inversion layers in metal-oxide-semiconductor systems with a high-kappa insulator: The role of remote phonon scattering," Journal of Applied Physics, vol. 90, pp. 4587-4608, 2001.
[19] S. Datta, G. Dewey, M. Doczy, B. Doyle, S. Hareland, B. Jin, et al., "High Mobility Si/SiGe Strained Channel MOS Transistors with HfO~ 2/TiN Gate Stack," in IEDM, 2003, pp. 653-656.
[20] R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, and M. Metz, "High-κ/metal-gate stack and its MOSFET characteristics," IEEE Electron Device Lett, vol. 25, pp. 408-410, 2004.
[21] R. Hegde, D. Triyoso, S. Samavedam, and B. White Jr, "Hafnium zirconate gate dielectric for advanced gate stack applications," Journal of applied physics, vol. 101, p. 074113, 2007.
[22] H.-S. Jung, S.-A. Lee, S.-h. Rha, S. Y. Lee, H. K. Kim, D. H. Kim, et al., "Impacts of Zr Composition in Gate Dielectrics on Their Crystallization Behavior and Bias-Temperature-Instability Characteristics," IEEE Transactions on Electron Devices, vol. 58, pp. 2094-2103, 2011.
[23] " Moore's Law: 2015 mouse brain has been reached.," 2015.
[24] D. T. Wang, "Real world technologies (Selected Coverage)," IEDM 2005, 2005.
[25] K. M. Mark Bohr, "Intel's Revolutionary 22 nm Transistor Technology," 2011.
[26] G. L. Rahul Deokar, Hitendra Divecha, Ruben Molina, and Chi-Ping Hsu – Cadence Design Systems, "FinFET challenges and solutions – custom, digital, and signoff," 2013.
[27] S. Tam, P.-K. Ko, and C. Hu, "Lucky-electron model of channel hot-electron injection in MOSFET's," IEEE Transactions on Electron Devices, vol. 31, pp. 1116-1125, 1984.
[28] W. Shockley, "Problems related to pn junctions in silicon," Solid-State Electronics, vol. 2, pp. 35IN961-60IN1067, 1961.
[29] J. S. E. Townsend, "The theory of ionization of gases by collision," 1910.
[30] D. K. Schroder, Semiconductor material and device characterization: John Wiley & Sons, 2006.
[31] Y. Ye, C.-C. Wang, and Y. Cao, "Simulation of random telegraph noise with 2-stage equivalent circuit," in Proceedings of the International Conference on Computer-Aided Design, 2010, pp. 709-713.
[32] R. Gusmeroli, C. M. Compagnoni, A. Riva, A. Spinelli, A. Lacaita, M. Bonanomi, et al., "Defects spectroscopy in SiO2 by statistical random telegraph noise analysis," in 2006 International Electron Devices Meeting, 2006, pp. 1-4.
[33] L. Hochul, C. Seongjae, and S. Hyungcheol, "Accurate extraction of the trap depth from RTS noise data by including poly depletion effect and surface potential variation in MOSFETs," IEICE transactions on electronics, vol. 90, pp. 968-972, 2007.
[34] C.-E. Chen, T.-C. Chang, B. You, W.-H. Lo, S.-H. Ho, C.-H. Dai, et al., "Investigation of Lateral Trap Position by Random Telegraph Signal Analysis in Moderate Inversion in n-Channel MOSFETs," ECS Solid State Letters, vol. 2, pp. Q90-Q92, 2013.
[35] Z. Çelik-Butler, P. Vasina, and N. V. Amarasinghe, "A method for locating the position of oxide traps responsible for random telegraph signals in submicron MOSFETs," IEEE Transactions on Electron Devices, vol. 47, pp. 646-648, 2000.
[36] S. Lee, H.-J. Cho, Y. Son, D. S. Lee, and H. Shin, "Characterization of oxide traps leading to RTN in high-k and metal gate MOSFETs," IEDM Tech. Dig, pp. 763-766, 2009.
[37] S. Yang, H. Lee, and H. Shin, "Simultaneous extraction of locations and energies of two independent traps in gate oxide from four-level random telegraph signal noise," Japanese Journal of Applied Physics, vol. 47, p. 2606, 2008.