隨著近年來可攜帶式電子產品需求的爆炸性增長以及物聯網和雲端應用的驅使下，為了滿足快速且大量的資料存取需求，半導體記憶體的發展已經成為近年來最受矚目的焦點之一，其中與邏輯製程相容之非揮發性記憶體由於可與積體電路整合於單晶片應用而受到廣泛討論，其中的一次性記憶體憑藉著其低功耗、高可靠性的優勢被廣泛應用於電子產品中作為重要參數儲存以及電路調校使用。
本論文提出了一種可應用於相容鰭式電晶體之一次性寫入記憶體的多階儲存單元操作方法。在本研究中使用的一次性寫入記憶體利用閘極介電層崩潰作為資料寫入方式，由於鰭式電晶體的尖角效應影響，使得一次性寫入記憶元的寫入電壓降低、寫入時間縮短。經由實驗發現，在資料儲存點的崩潰後電阻會受到崩潰瞬間通過電流影響，透過選擇電晶體的閘極電壓控制流過電流大小，擁有多階儲存能力的一次性寫入記憶體被成功應用於先進非揮發性記憶體上，和傳統一次性寫入記憶體最大的不同是一個記憶元可以寫入兩個位元，在讀取電壓僅有略為提升下使單位記憶元的儲存能力加倍，提升資料儲存密度，並且藉由長時間連續讀取以及長時間高溫烘烤測試得知其具有優異的資料保存能力以及干擾抵抗性，使其可以成功應用在先進非揮發性記憶體應用。

With the explosive growth of the demand for portable electronic products, internet of things, and cloud applications, the development of semiconductor memories has been the focus of much attention in these years. CMOS compatible embedded non-volatile memories have been widely introduced due to the high integration with integrated circuits. One-Time Programmable (OTP) memories with the benefits of low power and high reliability have been widely applied in parameter storage and circuit trimming.
A new operation scheme is proposed for achieving multi-level storage in FinFET OTP cells by high-κ metal gate (HKMG) CMOS process. This OTP cells programmed by breaking down of the gate dielectric layer, during which the corner effect in the FinFET structure shortens the program time and lowers program voltages. The after breakdown resistance in the storage node is found to be well controlled by the compliance current level set by the select transistor. Through the select gate voltage control, the multi-level OTP cell has been demonstrated for in advanced logic non-volatile memory (NVM) applications. Compare with the conventional OTP cell, MLC OTP allows the storage of two bits per cell. With only a slight increase in read voltage, the storage capacity of single cell is doubled. In addition, the superior data retention and disturbs immunity are verified by a long-term continuous read and baking under a high temperature. With these excellent properties, this new MLC OTP cells can be readily applied to conventional 2-level OTP memories for higher density applications.

摘要 i
Abstract ii
致謝 iii
內文目錄 iv
附圖目錄 vi
附表目錄 viii
第一章 序論 1
1.1 一次性寫入記憶體介紹及應用 1
1.2 一次性寫入記憶體最佳化方向 3
1.3 論文大綱 4
第二章 一次性寫入記憶體技術回顧與發展 6
2.1介電層電性崩潰式元件 6
2.2導電層熔毀式元件 9
2.3電荷儲存式元件 10
2.4小結 11
第三章 多階儲存單元一次性寫入記憶體元件結構與操作原理 17
3.1 元件結構與製程介紹 17
3.2 介電層電性崩潰 18
3.2.1 初始讀取電流 18
3.2.2 介電層電性崩潰與其理論模型 20
3.2.3 崩潰後之多階儲存單元之電性表現 22
3.3 元件操作機制及記憶體陣列架構 23
3.3.1 寫入機制 23
3.3.2 讀取機制 23
3.3.3 記憶體陣列架構 24
3.4 小結 24
第四章 多階儲存單元一次性寫入記憶體元件量測與分析 39
4.1 量測環境介紹 39
4.2 元件基本電性量測與操作條件最佳化 40
4.3 元件可靠度分析 42
4.3.1 資料保存性測試 42
4.3.2 讀取干擾測試 42
4.4 多階儲存單元一次性寫入記憶體元件特點與比較 43
4.5 小結 44
第五章 結論 57
參考文獻 58

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