本研究之目的在於將高動態範圍之像素陣列、二次相關取樣電路、類比數位轉換器以及週邊電路整合在一個晶片裡，使其能方便應用於現今的可攜式多功能消費電子產品。
傳統的單斜率類比數位轉換器架構以高線性度、架構簡單且低功率損耗的為其優點，相當適用於行並列的影像感測器輸出。因此本研究使用改良後的”二階段式”架構，相較於傳統單斜式架構擁有更快的轉換速度，可應用於未來更高畫素的電子產品中。電路設計的規格為十位元解析度，取樣頻率33kHz。
本研究使用標準的TSMC 0.18μm CMOS標準製程，實際下線晶片為64x36陣列，嘗試實踐一個具有高動態偵測範圍、30frame/s的畫面更新率的單晶片攝影系統。

The purpose of this work is to integrate photovoltage-sensing pixels, correlated double sampling circuit, analog-to-digital converter (ADC) and peripheral circuits in a single chip. Make it easily to be applied to multi-function consumer electronics.
Single-slope ADCs (SS ADC) are suitable for column-parallel CMOS image sensor readout architectures owing to their simplicity, high linearity and low power consumption. This work proposes a column-parallel two-step single-slope ADC (TSSS ADC) for high speed CMOS image sensor. The conversion speed of the proposed ADC is faster than conventional SS ADC. Therefore, TSSS ADCs can handle higher resolution consumer electronics. Designed resolution is 10bit, and the sampling rate is 33kHz.
A 64×36 image sensing pixel array was fabricated with TSMC 0.18 μm CMOS technology, based on the specifications of a Full HD camera-on-ship system with high dynamic range and 30 frames per second.

前言
研究背景與發展現況…………………………………………1
研究動機………………………………………………………3
論文章節架構…………………………………………………4
CMOS影像感測器之介紹與說明
2.1 CMOS影像感測器的基本原理與操作………………………….6
2.2 CMOS影像感測器的特性與參數……………………………….8
2.3 CMOS影像感測器常見之像素結構……………………………11
2.3.1被動式像素感測(Passive Pixel Sensor, PPS)………………12
2.3.2主動式像素感測(Active Pixel Sensor, APS)……………….12
2.3.3數位式像素感測(Digital Pixel Sensor, DPS)………………14
2.4類比數位轉換器的基本參數……………………………………14
2.5 CMOS影像感測器之類比數位轉換器………………..17
電路設計
3.1感光二極體設計…………………………………………………25
3.2像素陣列電路設計………………………………………………26
3.3相關二次取樣電路設計原理……………………………………27
3.4消除偏移量電路設計原理………………………………………28
3.5二階段式類比數位轉器設計原理………………………………30
3.5.1二階段式類比數位轉換器介紹……………………………30
3.5.2電路架構……………………………………………………31
3.5.3比較器……………………………………………………....34
3.5.4斜坡產生器…………………………………………………34
3.5.5計數器與移位暫存器………………………………….....36
3.6偏壓電路設計………………………………………………….38
3.6.1常數轉導偏壓電路(constant Gm bias circuit)…………...38
3.6.2帶差參考電路(bandgap reference circuit)……………….40
3.7時序電路設計………………………………………………….41
模擬結果
4.1像素電路模擬………………………………………………….44
4.2相關二次取樣電路模擬…………………………………….…46
4.3斜坡產生電路模擬…………………………………………….48
4.4二階段式ADC電路模擬……………………………….……..49
4.4.1動態參數測試……………………………….……………49
4.4.2靜態參數測試…………………………………………….51
4.5影像感測器數位輸出模擬…………………………………….52
4.6時脈控制電路模擬…………………………………………….54
4.7晶片佈局……………………………………………………….55
4.8模擬結果與文獻比較………………………………………….58
量測與討論
5.1量測系統的建立………………………………………………59
5.2量測結果………………………………………………………60
5.2.1偏壓電路及時脈控制…………………………………....60
5.2.2源極隨耦器線性度量測…………………………………62
5.2.3單一像素量測……………………………………………63
5.2.4 ADC量測………………………………………………...64
5.2.5 64×36陣列輸出量測………………………………...….68
5.2.6整體規格…………………………………………..……..69
5.3量測結果討論…………………………………………………69
總結
6.1成果整理………………………………………………………76
6.2後續研究改進之建議…………………………………………76

[1] Behzad Razavi, “Design of Analog CMOS Integrated Circuit”, McGraw-Hill, 2001.
[2] Abbas El Gamal and Helmy Eltoukhy, “CMOS IMAGE SENSORS”, IEEE Circuits Devices Mag., pp. 6-20, May June 2005.
[3] 劉冠言, “具有行並列十位元單斜率類比數位轉換器之影像感測器”, 國立清華大學, 電子工程研究所, 碩士論文, 中華民國一百零五年七月
[4] 蔡葳品, “應用於0.18um標準SiGe BiCMOS製程之Full HD影像感測器陣列電路設計”, 國立清華大學, 電子工程研究所, 碩士論文, 中華民國一百零三年七月
[5] Satoshi Yoshihara, Yoshikazu Nitta, Masaru Kikuchi, Ken Koseki, Yoshiharu Ito, Yoshiaki Inada, Souichiro Kuramochi, Hayato Wakabayashi, Masafumi Okano,Hiromi Kuriyama, Junichi Inutsuka, Akari Tajima, Tadashi Nakajima, Yoshiharu Kudoh, Fumihiko Koga, Yasuo Kasagi, Shinya Watanabe, and Tetsuo Nomoto, “A 1/1.8-inmos2V 6.4 MPixel 60 frames/s CMOS Image Sensor With Seamless Mode Change”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 12, pp. 2998-3006, DECEMBER 2006
[6] Stuart Kleinfelder, SukHwan Lim, Xinqiao Liu, and Abbas El Gamal,“A 10000 Frames/s CMOS Digital Pixel Sensor”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, pp. 2049-2059, DECEMBER 2001.
[7] M. Bigas, E. Cabruja, J. Forest, J. Salvi, “Review of CMOS image sensors”, Microelectronics Journal 37 (2006) 433–451.
[8] Eric R. Fossum, “CMOS Image Sensors:Electronic Camera-On-A-Chip” , IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 10, pp. 1689-1698, OCTOBER 1997.
[9] Shih-Chii Liu, Jorg Kramer, Giacomo Indiveri, Tobias Delbuck, and Rodney Douglas, “Analog VLSI: Circuits and Principles”, Massachusetts Institute of Technology, 2002.
[10] 何昆展,“矽鍺BiCMOS製程中整合類比數位轉換器之影像感測電路設計＂, 國立清華大學, 電子工程研究所, 碩士論文, 中華民國一百零一年七月
[11] Seunghyun Lim, Jeongwan Lee, Dongsoo Kim, and Gunhee Ham, “A High-Speed CMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 3, pp. 393-398, MARCH 2009.
[12] F. Azdis, S. Bernard, Y. Bertrand, X. Michel, M. Renovell, ”A Low-Cost Adaptive Ramp Generator for Analog BIST Applications,” 19th IEEE Pro. on VLSI Test Symposium, pp 266-271, 2001.
[13] “Noise” in Design of Analog CMOS Integrated Circuits, Behzad Razavi, 1st New York,USA: McGraw-Hill, 2001, ch.7 pp. 215-218, ch.11 pp. 377-381, ch.12 pp. 410-423.
[14] C. Lee, P. Mok, “A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique”, IEEE Journal of Solid-State Circuits, vol.39, pp.3-14, Jan. 2004.
[15] M. F. Snoeij, P. Donegan, A. J. P. Theuwissen, K. A. A. Makinwa, and J. H. Huijsing, “Multiple-ramp column-parallel ADC architectures for CMOS image sensors,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2968–2976, Dec. 2007.