時序臆測技術常被用來設計高效能的電路，他考慮設計中發生的平均情況 (average-case) 來做時序的最佳化。有別於傳統時序的最佳化，通常考慮設計中可能發生的最糟情況 (worst-case)，但是這些最糟情況在運作中極少發生，這導致傳統最佳化的方法在資源運用上並不有效。可變動時脈設計(variable latency design, VLU) 是時序臆測技術中的一種。
在先進製程技術下，變動性 (variability) ─如製程、電壓、和溫度變化 (PVT variations) 已經是造成晶片設計發生錯誤的重要原因。製程、電壓、和溫度變化所造成的時序 (timing) 不確定性，會使得電路設計不符合所要求的時序規格(timing specification)，傳統可變動時脈電路設計可以使用最糟情況設計風格 (worst-case design style)來解決此一問題，也就是預留額外時序，但其效能會因此下降。
在本論文中，我們提出一個基於感測器的可變動時脈設計 (sensor-based variable latency design, S-VLU) 來增加設計的效能。此基於感測器的可變動時脈設計透過在電路上擺放感測器，來偵測電路上的訊號改變 (transition)，可以根據實際上的製程、電壓、和溫度變動性所造成的時序變化，來決定是否要給電路額外時間來完成此次運算。實驗證明，在考慮製程、電壓、和溫度變動性下，我們提出的設計相較於不可變動時脈設計 (也就是，使用最糟情況時序最佳化且用預留額外時序來解決製程、電壓、和溫度變化所造成的時序不確定性的設計)，可以達到20.82% 效能增進，而傳統可變動時脈設計則是 -6.67% 效能增進。很明顯，傳統可變動時脈設計在考慮時序變動性下，效能急遽下降，糟於不可變動時脈設計。

Time speculation has been widely used to achieve high performance in modern design as it uses the strategy of average-case timing optimization instead of worst-case timing optimization focusing on reducing worst-case path delay which rarely happens. Variable-latency design style is one research category of time speculation. As the variations in process and environment are hard to predict, the conventional variable-latency units (VLUs) designed at pre-silicon stage will experience significant performance loss. In this paper, we propose a novel sensor-based VLU (S-VLU) adapting to PVT variations and alleviating the floating mode problem of hold logic by using in-situ sensors to obtain real-time transition information in circuit. The S-VLU can achieve much higher accuracy. Moreover, we also propose a sensor placement strategy to achieve near-maximal performance gain. Experimental results on tsmc 40nm ISCAS designs show that the S-VLU achieves a 20.82% performance improvement as compared to a -6.67% improvement of traditional hold logic. The area overhead of the S-VLU is 18% compared to 15.2% of traditional hold logic. To the best of the authors’ knowledge, this is the first wok to address PVT variations in VLD.

List of Contents
List of Contents VI
List of Figures VII
List of Tables VIII
CHAPTER 1 INTRODUCTION 1
CHAPTER 2 PRELIMINARIES 5
2.1 Hold Logic Generation 5
2.1.1 Concept of Hold Logic 5
2.1.2 Hold Logic in [13] 6
2.2 Problem of false positives 8
2.3 Transition Detector 10
CHAPTER 3 SENSOR-BASED VLU (S-VLU) 12
3.1 S-VLU Concept 12
3.2 S-VLU Architecture 14
3.3 S-VLU Construction 15
3.4 S-VLU Accuracy 17
3.4.1 PVT variations 17
3.4.2 The assumption of floating mode 19
CHAPTER 4 ALGORITHM 21
4.1 Sensor Placement Strategy 21
4.2 S-VLU Generation 24
CHAPTER 5 EXPERIMENTAL RESULTS 26
CHAPTER 6 CONCLUSIONS 29
REFERENCES 30

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