就地時序(timing)錯誤偵測及改正方法(例:Razor)可以偵測在電路中路徑的效能，尤其是對於考慮局部變動性的適應性電壓調變系統(Adaptive Voltage Scaling)更加有彈性。然而Razor存在著短路徑(short path)問題，在更先進的製程上加入延遲裝置(buffer)是不適合的，因此預錯誤(pre-error)偵測就被提出來替代。除此之外，複雜的錯誤改正(error correction)也不再需要。他們假設輸入樣式(input patterns)產生的延遲都是呈現高斯分布(Gaussian distribution)，因此馬克夫鏈模型(Markov chain model)被提出來在預錯誤適應性電壓調變(pre-error AVS)控制器去尋找品質跟功率的平衡點。對於可容忍錯誤(error-tolerant)的應用上，預錯誤適應性電壓調變是比使用以Razor為基底的電壓調變還要更有效率。在本論文中，我們在28奈米製程下的可調變電壓現場可程式化閘陣列(Field-Programmable Gate Array)建構了預錯誤適應性電壓調變系統，我們觀察到當延遲分布是跟隨時間變動(time-varying)且是非高斯分布，過於樂觀電壓調變(overoptimistic voltage scaling)會發生且可能導致嚴重的錯誤。為了解決過於樂觀電壓調變的問題，我們提出插入某些邏輯閘去收集延遲嚴重的資訊，而這些資訊將會送入我們的Q適應學習模組去建構Q適應學習適應性電壓調變(learning-based AVS)。實驗結果顯示，我們提出的方法在給隨機輸入樣式時可以比原先假設延遲是高斯分布的預錯誤適應性電壓調變省下10.50%的功耗及降低0.16%的錯誤率;而當給非隨機輸入樣式時也可以省下12.51%的功耗及降低0.06%的錯誤率。

In-situ timing error detection and correction mechanisms (such as Razor) monitor the performance of actual datapaths, and are believed more resilient in adaptive voltage scaling (AVS) systems, especially when considering local variations. However, Razor has serious hold time problems, of which the overwhelming buffer padding makes it infeasible in advanced process technologies. Pre-error (or in-situ canary) detection was then proposed as an alternative. In addition, sophisticated error correction is no longer needed accordingly. The Markov chain model was proposed by independent researchers to design the pre-error AVS controller to explicitly trade quality for energy, where the input patterns are assumed to have a Gaussian delay distribution. For error-tolerant applications where few errors are acceptable, pre-error AVS is shown more efficient than Razor-based approaches. In this paper, a pre-error AVS system has been constructed on a 28nm FPGA platform with programmable power supply. It is observed that when the delay distributions are time-varying and non-Gaussian, overoptimistic voltage scaling (OVS) can occur and may lead to serious problems in pre-error AVS. To resolve the OVS problem, we propose to insert certain logics to collect the delay criticality information, which is fed into a Q-learning model to create the learning-based AVS. Experimental results show that the proposed scheme saves 10.50% power while reducing 0.16% error rate for random inputs and saves 12.51% power while reducing 0.06% error rate for non-random inputs, compared with the original pre-error AVS that assumes a static Gaussian delay distribution.

CHAPTER 1 INTRODUCTION 1
CHAPTER 2 PRE-ERROR AVS 5
CHAPTER 3 PRE-ERROR AVS ON FPGA MULTIMEDIA PROCESSING 9
CHAPTER 4 LEARING-BASED AVS 14
4.1 Path Definition 14
4.2 Pattern Classification 15
4.3 Q-Learning 18
CHAPTER 5 EXPERIMENTAL RESULTS 21
CHAPTER 6 CONCLUSIONS 26
REFERENCES 27

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