FPGA 仿 真 系 統 對 於 邏 輯 驗 證 來 說 非 常 重 要，它 比 使 用 軟 體 模 擬 器 的 速度 來 得 快 速。它 是 由 多 個 FPGA互 相 連 結 而 成 的 系 統，我 們 可 以 將 要 模 仿 的 邏 輯 電 路 做 切 割 並 映 成 到 系 統 上 的 FPGA上 來 進 行 模 擬 。 然 而 當 有 一 條 訊 號 路 徑 通 過 FPGA與 FPGA 之 間 的 連 接 時，它 的 延 遲 時 間 會 是 一 條 訊 號 路 徑 通 過 一 個 FPGA 的 2 到 4 倍 慢 。 而 我 們 的 研 究 則 是 透 過 複 製 邏 輯 元 件 的 方 式 ， 來 使 整 個 系 統 的 效 能 提 升 。 就 實 驗 結 果 來 看 ， 我 們 可 使 效 能 比 原 來 的 效 能 提 升 大 約 9 % 。

Field Programmable Gate Array (FPGA) emulation systems are important for logic verification. This approach is faster than software simulators and hardware accelerators. FPGA emulation systems are made up of interconnected FPGAs. Logic designs can be partitioned into small circuits and mapped onto an FPGA emulation system in order to implement the design.
However, delays of the path pass through connections between FPGAs is approximately 2x to 4x slower than the delay of the path pass through single FPGA. In this work, we present an algorithm to replicate logic components to improve performance. Experiment results demonstrate that this can reduce delays (i.e., improve performance) by as much as 9%

Abstract i
1 Introduction 1
1.1 LogicReplication............................... 1
1.2 RelatedWorks................................. 3
1.3 OurContributions............................... 4
1.4 Organization.................................. 4
2 Preliminaries 5
2.1 Timingmodel................................. 5
2.2 Timinganalysis................................ 6
2.3 ProblemFormulation............................. 7
3 Algorithm 9
3.1 OverallFlow................................. 9
3.2 FindShortestDelayPath........................... 11
3.3 CandidateLUTsSelection.......................... 11
3.4 DynamicProgrammingforLUTsReplication................ 13
3.5 Flip-flopreplication.............................. 18
4 Experiment 20
4.1 LUTsreplication............................... 22
4.2 Flip-flopsreplication............................. 23
4.3 LUTSandflip-flopsreplication........................ 24
5 Conclusion..............26

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