一個複雜的布林函數只需要一個臨界值邏輯閘即可表示，這是臨界值邏輯閘重要的特性。
近年來，許多研究著重在如何將布林函數合成為臨界值邏輯電路。
在此篇論文中，我們提出以正規方法運用於臨界值邏輯電路之優化的研究。
我們的方法由分解邏輯電路(network decomposition)及可滿足性為基礎的最佳化方法(SAT-based optimization)所組成。
在此篇論文中，我們也提出更實際的成本函數計算-以臨界值邏輯電路中的臨界值邏輯閘的個數、權重以及臨界值的總和為計算依據。
我們以IWLS 2005的效能評估程式來進行實驗。
實驗結果顯示我們提出的演算法可以平均減少將近6%的成本。

Threshold logic has a property that it can represent a complex Boolean function with one threshold logic gate.
Recently, many works have focused on the synthesis of threshold logic networks from the Boolean functions.
In this paper, we propose a formal approach to the threshold logic network optimization.
The proposed approach consists of network decomposition and SAT-based optimization based on a more practical cost function -- the summation of gate counts, weights, and threshold values in the whole threshold network.
We conducted the experiments on a set of IWLS 2005 benchmarks.
The experimental results show that the proposed algorithm can effectively reduce the cost by nearly 6% for the benchmarks on average.

中文摘要i
Abstract ii
Acknowledgement iii
Contents iv
List of Tables vi
List of Figures vii
1 Introduction 1
2 Preliminaries 5
2.1 Positive-negative Weight Transformation 5
2.2 Critical-Eect Vectors 5
2.3 Hyperplane and Half-space 6
3 Network Decomposition 8
4 SAT-based Optimization 11
4.1 An Example 11
4.2 Function Derivation from the CEVs 12
4.3 SAT-based Optimization 12
4.3.1 AND-phase 13
4.3.2 OR-phase 14
4.4 Weights and Threshold Values Update 15
4.4.1 AND-phase 15
4.4.2 OR-phase 16
5 Overall Algorithm 17
6 Experimental Results 19
7 Conclusion 23

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