隨著製程不斷演進，自對準雙重圖案成為未來有希望的微影技術之一。現有針對自對準雙重圖案的研究大部分都集中在佈局分解和繞線上，只有非常少的研究是在擺置階段。然而，在最終佈局上針對不利自對準雙重圖案進行修改非常困難，因此，如何在擺置階段時得到一個對自對準雙重圖案友善的佈局非常重要。
在本篇論文中，我們針對自對準雙重圖案改善標準元件細部擺置的問題進行研究，此問題要求對細部擺置進行改善並及找出合法自對準雙重圖案佈局分解，使得疊加層違反量以及線長能越小越好。在以空白空間插入和元件翻轉的技術之下，我們提出一個方法解決此問題。實驗結果顯示我們所提出的演算法具有良好的效益。

As process nodes continue to shrink, self-aligned double pattern (SADP) has become one of the most promising techniques for advanced lithography. Existing works for SADP focus more on layout decomposition and routing, while very few attempts are on placement. However, modifying SADP unfriendly patterns in a final layout requires high efforts, so how to generate an SADP friendly layout in an early physical design stage such as placement becomes important.
In this thesis, we study the problem of refining a standard cell placement for SADP, which asks to simultaneously refine a detailed placement and find a valid SADP layout decomposition such that both overlay violation and wirelength are as small as possible. Based on the techniques of white space insertion and cell flipping, we propose an approach to the addressed placement refinement problem. Experimental results show the efficacy of our approach

1 Introduction 1
2 Preliminaries and Problem Formulation 4
2.1 Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Review of SADP-aware Single-row Placement Algorithms 6
3.1 Construction of Cell Solution Graph . . . . . . . . . . . . . . . . . . 6
3.2 Construction of Cell Boundary Solution Graph . . . . . . . . . . . . . 9
3.3 SADP-aware Single-Row Placement Algorithms . . . . . . . . . . . . 10
3.3.1 Algorithm with White Space Insertion . . . . . . . . . . . . . 10
3.3.2 Algorithm with White Space Insertion and Cell Flipping . . . 14
3.3.3 Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 SADP-aware Placement Renement Algorithms 16
4.1 Renement for SADP Decomposition . . . . . . . . . . . . . . . . . . 16
4.2 Renement for Wirelength Minimization . . . . . . . . . . . . . . . . 17
5 Experimental Results 22
6 Conclusion 27

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