對於低功耗且多異質組件的積體電路而言，以矽載板為中介層之二點五維積體電路與扇出晶元級封裝提供可行的多裸晶整合技術。然而，為了獲得較可靠的多裸晶整合晶片，許多不同的設計問題仍待解決。此外，就一個有諸多匯流排的多裸晶整合晶片而言，要如何規劃裸晶之間的匯流排連線亦是個非常重要且具挑戰的設計工作。
在本論文，我們提出數個針對以矽載板或扇出晶元級封裝為實現平台之多匯流排、多裸晶整合晶片設計的方法，包括如何擺置多個裸晶、如何指定矽穿孔(就矽載板而言)或是錫球(就扇出晶元級封裝而言)的訊號，以及如何漸進地改善擺置及指定訊號的結果，實驗結果顯示我們提供的方法針對多匯流排的設計是友善的、漸進式的改善是有效的，以及加速的效果是非常顯著的。

Interposer-based 2.5D-IC and fan-out wafer level packaging (FO-WLP) technologies are becoming attractive and viable multi-die integration solutions for designs that require lower power and heterogeneous components. However, to make a highly integrated multi-die IC reliable, various design issues remain to be solved. In addition, for a bus-rich multi-die IC, how to plan inter-die bus connections is also an important and challenging design task.

In this thesis, we propose several methods for bus-rich designs each of which consists of multiple dies integrated on a platform that could be a silicon interposer or FO-WLP. These methods include how to place a set of dies on the platform, how to assign signals to TSVs (for the interposer case) or solder balls (for the FO-WLP case), and how to iteratively refine the placement and signal assignment results. The experimental results show that the proposed methods are friendly to bus-rich designs, the refinement process is effective, and the speedup is significant when the proposed acceleration techniques are used.

1 Introduction 1
2 Preliminaries 5
2.1 Wirelength Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Review of A Previous Work . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.1 Enumeration-based Floorplanning Algorithm . . . . . . . . . . 8
2.3.2 Signal Assignment Algorithm . . . . . . . . . . . . . . . . . . 10
3 Our Methodology 14
3.1 Initial Multi-die Placement . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Initial Signal Assignment . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.1 ILP-based Signal Grid Assignment . . . . . . . . . . . . . . . 17
3.2.2 Network-
ow based Signal Assignment . . . . . . . . . . . . . 18
3.3 Incremental Renement . . . . . . . . . . . . . . . . . . . . . . . . . 21
4 Experimental Results 25
4.1 Results of Initial Multi-die Placement . . . . . . . . . . . . . . . . . . 26
4.2 Results of Initial Signal Assignment and Iterative Renement . . . . . 28
4.3 Comparison between our Methodology and [1] . . . . . . . . . . . . . 28
5 Conclusion 34

[1] W.-H. Liu, M.-S. Chang, and T.-C. Wang, "Floorplanning and signal assignment for silicon
interposer-based 3d ics," in Proc. of Design Automation Conference, 2014.
[2] M. Sunohara, T. Tokunaga, T. Kurihara, and M. Higashi, "Silicon interposer with tsvs
(through silicon vias) and fine multilayer wiring," in Proc. of Electronic Components and
Technology Conference, pp. 847-852, 2008.
[3] I. Limansyah, M. J. Wolf, A. Klumpp, K. Zoschke, R. Wieland, M. Klein, H. Oppermann,
L. Nebrich, A. Heinig, A. Pechlaner, H. Reichl, and W. Weber, "3d image sensor sip with tsv
silicon interposer," in Proc. of Electronic Components and Technology Conference, pp. 1430-
1436, 2009.
[4] M. Hogan, "Silicon interposer: Building blocks for 3d-ics," in Solid State Technology, vol. 54,
pp. 18-19, 2011.
[5] P. McLeelan, "2 1/2d integrated circuits," in DAC Knowledge Center, 2011.
[6] X. Inc., "Xilinx stacked silicon interconnect technology delivers breakthrough fpga capacity,
bandwidth, and power efficiency," in White paper: Virtex-7 FPGAs, 2010.
[7] C. C. L. et al., "High-performance integrated fan-out wafer level packaging (info-wlp): technol-
ogy and system integration," in Proc. of International Electronic Devices Meeting, pp. 14.1.1-
14.1.4, 2012.
[8] S. W. et al., "Fanout
ipchip ewlb (embedded wafer level ball grid array) technology as
2.5d packaging solutions," in Proc. of Electronic Components and Technology Conference,
pp. 1855-1860, 2013.
[9] F. Rafiq, M. C. Jeske, H. H. Yang, and N. Sherwani, "Integrated
oorplanning with buffer-/channel insertion for bus-based microprocessor designs," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 730-741, 2003.
[10] H. Xiang, X. Tang, and M. D. F. Wong, "Bus-driven
oorplanning," in IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, pp. 1522-1530, 2004.
[11] T.-C. Chen and Y.-W. Chang, "Modern
oorplanning based on b*-tree and fast simulated
annealing," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Sys-
tems, vol. 25, pp. 637-650, 2006.
[12] H. M. et al., "Rectangle packing based module placement," in Proc. of International Confer-
ence on Computer-Aided Design, pp. 479-482, 1995.
[13] Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu, "B*-trees: A new representation for
non-slicing
oorplans," in Proc. of Design Automation Conference, pp. 458-463, 2000.
[14] J. H. Law and E. F. Y. Young, "Multi-bend bus driven
oorplanning," in Integration, the
VLSI Journal, pp. 306-316, 2008.
[15] T. Ma and E. F. Y. Young, "Tcg-based multi-bend bus-driven
oorplanning," in Proc. of Asia
and South Pacific Design Automation Conference, pp. 192-197, 2008.
[16] P.-H. Wu and T.-Y. Ho, "Bus-driven
oorplanning with bus pin assignment and deviation
minimization," in Integration, the VLSI Journal, pp. 405-426, 2012.
[17] P.-H.Wu and T.-Y. Ho, "Bus-driven
oorplanning with thermal consideration," in Integration,
the VLSI Journal, pp. 369-381, 2013.
[18] W. Sheng and S. Dong, "Multi-bend bus-driven
oorplanning considering fixed-outline con-
straints," in Integration, the VLSI Journal, pp. 142-152, 2013.
[19] D. J.-H. Huang and A. B. Kahng, "Partitioning-based standard-cell global placement with an
exact objective," in Proc. of International Symposium on Physical Design, pp. 18-25, 1997.
[20] lp solve 5.5. http://lpsolve.sourceforge.net/5.5/.
[21] LEDA. http://cad-contest-2016.el.cycu.edu.tw/problem"_C/default.html.