近年，以非揮發記憶體(Non-volatile Memory, NVM) 來取代傳統的動態隨機存取記憶體(Dynamic Random Access Memory, DRAM) 當作主記憶體(Main Memory) 的架構經常被提出。由於非揮發記憶體在發生系統故障或是沒有電源供應的情況下還是能夠保存資料，故非常適合用來解決常被用在儲存和處理大數據(Big data)資料的內存資料庫(In-memory database)在意外發生所產生的運算、資料復原的問題。為了配合非揮發記憶體的特性，有一些方法提出在演算法上修改B+樹，以增加讀取的數量來減少寫入的數量的方式達到更好的效能。但與他們不同的是，我們提出了一個考慮快取記憶體(Cache) 的優化樹，稱作xB+-tree。 xB+-tree將會在處理插入和讀取資料時使用我們的存取區域性方法來減少每次處理資料時所需讀取或寫入的以一個快取記憶體塊為單位的資料量。實驗結果指出，xB+-tree比 Unsorted leaf 方法在插入資料時的總執行時間快33.48%，且在讀取資料時的總執行時間快2.74到3.16%。另一方面，xB+-tree也比 wB+-tree 方法在插入資料時快上43.48%，且在讀取資料時的總執行時間可達到6.98%。

The non-volatile main memory architecture is often proposed, because it can solve the problem of data storage of in-memory database when encountering a system failure (e.g., system crash, power failure). To achieve fast execution time, we proposed a cache-optimized tree, referred to as xB+-tree. It focuses on access the smallest number of cache lines and reduce the cache miss rate by using access-locality in insertion and query operations. The experimental results show that compared with previous unsorted leaf scheme, xB+-tree achieves up to 33.48% speedups for insertion and up to 2.74-3.16% speedups for query; compared with previous wB+-tree scheme, xB+-tree achieves up to 43.48% speedups for insertion and up to 6.98% speedups for query.

摘要 i
Abstract ii
1. Introduction 1
2. Background and Motivation 4
3. Access-Locality-Aware Cache-Optimized Tree 10
3.1 Overview 10
3.2 Write-Locality-Aware Insertion 11
3.3 Read-Locality-Aware Query 12
3.3.1 Multi-Frequency Bitmap 12
3.3.2 Aging 14
3.3.3 Query Locality 16
3.3.4 Split / Merge 18
4. Performance Evaluation 21
4.1 Experimental Setup 21
4.2 Experimental Results 23
4.2.1 Execution Time 23
4.2.2 Access Count 27
4.2.3 CPU Time 30
4.2.4 Access Data Distribution Sensitivity Analysis 31
5. Conclusion 33
6. References 34

[1] Rand Fishkin. (2009, Nov.) Illustrating the Long Tail. [Online]. https://moz.com/blog/illustrating-the-long-tail
[2] Shivaram Venkataraman, Niraj Tolia , Parthasarathy Ranganathan , and Roy H. Campbell , "Consistent and Durable Data Structures for Non-Volatile Byte-Addressable Memory," in FAST, 2011.
[3] Jun Yang, Qingsong Wei, Cheng Chen, Chundong Wang, and Khai Leong Yong, "NV-Tree: Reducing Consistency Cost for NVM-based Single Level Systems," in FAST, 2015, pp. 167-181.
[4] Shimin Chen and Qin Jin, "Persistent B+-Trees in Non-Volatile Main Memory," VLDB Endowment, vol. 8, no. 7, pp. 786-797, 2015.
[5] Andreas Chatzistergiou, Marcelo Cintra, and Stratis D. Viglas, "REWIND: Recovery Write-Ahead System for In-Memory Non-Volatile Data-Structures," VLDB Endowment, vol. 8, no. 5.
[6] Shimin Chen, Phillip B. Gibbons, and Suman Nath, "Rethinking Database Algorithms for Phase Change Memory," in CIDR, 2011.
[7] Weiwei Hu, Guoliang Li, Dalie Sun, and Kian-Lee Tan, "Bp-Tree: A Predictive B+-Tree for Reducing Writes on Phase Change Memory," in TKDE, 2014.
[8] Jun Rao and Kenneth A. Ross, "Making B+-Trees Cache Conscious in Main Memory," in SIGMOD, 2000.
[9] IG-HOON LEE, SANG-GOO LEE, and JUNHO SHIM, "Making T-Trees Cache Conscious on Commodity Microprocessors," JISE, vol. 27, pp. 143-161, 2011.
[10] Ig-hoon Lee, Junho Shim, Sang-goo Lee, and Jonghoon Chun, "CST-Trees: Cache Sensitive T-Trees," in DASFAA, 2007, pp. 398-409.
[11] Jun Rao and Kenneth A. Ross, "Cache Conscious Indexing for Decision-Support in Main Memory," in VLDB, 1999.
[12] Ping Chi, Cong Xu, Tao Zhang, Xiangyu Dong, and Yuan Xie, "Using Multi-Level Cell STT-RAM for Fast and Energy-Efficient Local Checkpointing," in ICCAD, 2014.
[13] Hung-Sheng Chang, Yuan-Hao Chang, Tei-Wei Kuo, and Hsiang-Pang Li, "A Light-Weighted Software-Controlled Cache for PCM-based Main Memory Systems," in ICCAD, 2015.
[14] Wei-Kai Cheng, Yen-Heng Ciou, and Po-Yuan Shen, "Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration," Elsevier, pp. 191-199, 2015.
[15] Namhyung Kim, Junwhan Ahn, Woong Seo, and Kiyoung Choi, "Energy-Efficient Exclusive Last-Level Hybrid Caches Consisting of SRAM and STT-RAM," in VLSI-SoC, 2015, pp. 183 - 188.
[16] Richard A. Hankins and Jignesh M. Patel, "Effect of Node Size on the Performance of Cache-Conscious Indices," in SIGMETRICS, 2003, pp. 283-294.
[17] Shimin Chen, Phillip B. Gibbons, and Todd C. Mowry, "Improving Index Performance through Prefetching," in SIGMOD, 2001.
[18] Ping Chi, Wang-Chien Lee, and Yuan Xie, "Making B+-Tree Efficient in PCM-Based Main Memory," in ISLPED, 2014.
[19] The gem5 Simulator. [Online]. http://gem5.org/