三維積體電路被認為是可以克服晶片電晶體數量不足問題的方法，三維積
體電路是利用矽穿通道來做晶粒的推疊，讓訊號可以在晶片上垂直地傳輸。但是晶片在運作時可能導致矽穿通道的毀壞，因此，可靠性在設計時是很重要的議題。容錯矽穿通道設計是一個提升可靠性的有效方法。在這篇論文中，我們會根據效率與成本來研究各種容錯矽穿通道設計的權衡取捨。為了讓可靠性的測量更具有真實性，我們提出了一個新的標準「修復率」來評估容錯矽穿通道設計的好壞。此外，為了設計一個更靈活且更有效的架構，我們加強環狀結構設計 [1]，讓這個架構可以調整大小以及容錯矽穿通道的比例。

Three-dimensional Integrated Circuits (3D-ICs) is a next-generation technology that could be a solution to overcome scaling problem. It stacks dies with Through-Silicon Vias (TSVs) so that signals can transmit through dies vertically. TSV may fail when a chip is working. Hence, reliability is an important issue in design time. TSV redundancy is one of effective methods to enhance reliability. In this paper, we will study the tradeoff of various TSV redundancy architectures in terms of effectiveness and cost. To allow the measurement of reliability more realistic, we propose a new standard, repair rate, to appraise the TSV redundancy architectures. Moreover, to design a more flexible and efficient structure, we enhance the ring-based architecture [1] that can adjust grid size and TSV redundancy.

1 Introduction 1
2 Reliability 4
2.1 Metric for reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Motivation and objective . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Evaluation Flow 8
4 Enhancement of Ring-based Architecture 11
4.1 The number of Redundant TSVs and repair rate . . . . . . . . . . . . 11
4.2 Two methods for MUX-area cost reduction . . . . . . . . . . . . . . . 13
5 Evaluation of Four Redundancy Architectures 17
6 Conclusions 24

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