帳號:guest(13.58.139.190)          離開系統
字體大小: 字級放大   字級縮小   預設字形  

詳目顯示

以作者查詢圖書館館藏以作者查詢臺灣博碩士論文系統以作者查詢全國書目
作者(中文):鄭至捷
作者(外文):Zheng, Chih Chieh
論文名稱(中文):Online Slack-Time Binning for IO-Registered Die-to-Die Interconnects
論文名稱(外文):用在具有輸入與輸出暫存器的裸晶連接線的線上寬裕時間分組方法
指導教授(中文):黃錫瑜
指導教授(外文):Huang, Shi Yu
口試委員(中文):蒯定明
趙家佐
周永發
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學號:103061604
出版年(民國):105
畢業學年度:104
語文別:英文
論文頁數:38
中文關鍵詞:寬裕時間建立時間線上監測可靠度時序故障威脅
外文關鍵詞:slack-timesetup-timeon-line monitoringreliabilitytiming failure threat
相關次數:
  • 推薦推薦:0
  • 點閱點閱:358
  • 評分評分:*****
  • 下載下載:0
  • 收藏收藏:0
在現今的晶片製造中,將多塊裸晶進行堆疊而形成多裸晶整合晶片變得越來越受重視,因其具有如將多種製程的裸晶進行異質整合、較小的尺寸、高良率的潛力等等優勢。在多裸晶整合晶片中,裸晶之間的連接線的輸入輸出端通常都會設有暫存器,因為其長度可能會變得非常長,導致訊號通過這些連線的延遲大幅增加,並且這些連接線會由許多不同的材料構成而變得相當複雜,很容易就會受到製造瑕疵以及環境壓力造成的性能惡化的影響,這個現象導致在可靠度優先的應用中,需要使用線上性能監測方法來確保晶片能夠正確運作。在這篇論文中,我們提出了一種寬裕時間分組方法(slack-time binning scheme),透過這個方法能夠持續的監測具有輸入與輸出暫存器的裸晶之間的連接線可能發生的時間延遲錯誤。這個方法透過將一個個寬裕時間監測器安置在需要監測的裸晶間連接線接收端的正反器上,能夠在不干擾、中斷電路正常運作的情況下,於背景安靜地監測各個接收端的寬裕時間。我們將會提出兩項針對傳統時序違規檢查器的改進技術:(1)可調變式的保護區域,(2)偏移量補償電路。透過這兩項機制設計而成的寬裕時間監測器,達到我們所提出的線上寬裕時間分組方法。實驗結果指出此種方法能夠追蹤到裸晶間連接線的寬裕時間差異,而每一條待監測的連接線增加的額外面積花費相當於2.35個邊界掃描電路的大小。
In a today's multi-die integrated IC, the die-to-die interconnects are often complicated and susceptible to various kinds of manufacturing defects and stress-induced performance degradation in the field. This phenomenon has prompted a need to perform online monitoring of the signal integrity over the die-to-die interconnects for reliability critical applications. In this work, we present a slack-time binning scheme so that one can quantify the margin of a timing failure threat (TFT) occurring to a registered die-to-de interconnect constantly. The proposed scheme attaches a Slack-Time Monitor (ST-monitor) to each Flip-Flop (FF) that receives a signal transmitted through a die-to-die interconnect under monitoring. Two techniques are introduced to enhance the traditional "Timing-Violation Checker", namely (1) tunable guard-band technique, and (2) offset compensation technique. With these two techniques, one can thereby perform online slack-time binning. Experimental results using a 90nm CMOS process show that the proposed scheme has a low area overhead of only approximately 2.35 times the area of a boundary scan cell.
Abstract i
摘要 ii
誌謝 iii
Content iv
List of Figures v
List of Tables vii
Chapter 1 Introduction 1
1.1 Introduction 1
1.2 Thesis Organization 4
Chapter 2 Preliminaries 5
2.1 Slack-time 5
2.2 Basic Timing-Violation Checker 6
2.3 Related work 7
Chapter 3 Proposed Slack-Time Monitoring Scheme 10
3.1 Basic Slack-Time Monitor 11
3.2 Basic Guard-Band Checking Principle 15
3.3 Progressive Guard-Band Binning Flow 17
3.4 Offset Compensation 19
Chapter 4 Experimental Results 24
4.1 Process Variation 28
4.2 Area overhead 32
Chapter 5 Conclusion 34
References 35

[1] T. Frank, S. Moreau, C. Chappaz, L. Arnaud, P. Leduc, A. Thuaire, and L. Anghel, "Electromigration Behavior of 3D-IC TSV Interconnects," Proc. of IEEE Electronic Component and Technology Conf. (ECTC), pp.326-330, June 2012.
[2] T. Frank, C. Chappaz, P. Leduc, L. Arnaud, F. Lorut, S. Moreau, A. Thuaire, R. El Farhane, and L. Anghel, “Resistance Increase Due to Electromigration Induced Depletion under TSV," Proc. of IEEE Int'l Reliability Physics Symp. (IRPS), pp. 3F.4.1-3F.4.6, April 2011.
[3] K. H. Lu, S.-K. Ryu, Q. Zhao, X. Zhang, J. Im, R. Huang, and P. S. Ho, “Thermal Stress Induced Delamination of Through Silicon Vias in 3D Interconnects," Proc. of IEEE Electronic Component and Technology Conf. (ECTC), pp. 40-45, June 2010.
[4] P. Lall, K. Mirza, and J. Shuling, "Damage Pre-Cursor Based Life Prediction of the Effects of Mean Temperature of Thermal Cycle on the SnAgCu Solder Joint Reliability," Proc. of Electronic Components and Technology Conf. (ECTC), pp. 990-1003, 2014.
[5] U. Kang, H. Chung, S. Heo, D. Park, H. Lee, J. Kim,S. Ahn, S. Cha, J. Ahn, D. Kwon, et al.,“8 GB 3-D DDR3 DRAM using Through-Silicon-Via Technology,” IEEE Journal of Solid-State Circuits, Vol. 45, No. 1, pp. 111–119, 2010.
[6] A. Hsieh, T. Hwang, M. Chang, M. Tsai, C. Tseng, and H.-C. Li, “TSV redundancy: Architecture and Design Issues in 3D IC,” Proc. of IEEE Design, Automation, and Test in Europe, pp. 166-171, March 2010.
[7] L. Jiang, F. Ye, Q. Xu, K. Chakrabarty, and B. Eklow, "On Effective and Efficient In-Field TSV Repair for Stacked 3D ICs," Proc. of Design Automation Conf, pp. 1-6, 2013.
[8] C. Serafy and A. Srivastava, "Online TSV Health Monitoring and Built-In Self-Repair to Overcome Aging," Proc. of IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp. 224-229, 2013.
[9] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, “Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 2, pp. 333-343, Feb. 2012.
[10] K. Chakrabarty, “TSV Defects and TSV-Induced Circuit Failures: The Third Dimension in Test and Design-for-Test,” Proc. of Int’l Reliability Physics Symp., (IRPS), pp. 5F1.1-5F.1.12, 2012.
[11] Y. J. Huang, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “A Built-In Self-Test Scheme for the Post-Bond Test of TSVs in 3D ICs,” Proc. of IEEE VLSI Test Symp, pp. 20-25, 2011.
[12] Y.-H. Lin, S.-Y. Huang, K.-H. Tsai, W.-T. Cheng, S. Sunter, Y.-F. Chou, and D.-M. Kwai, “Small Delay Testing for TSVs in 3D ICs,” IEEE Proc. of Design Automation Conf., June 2012.
[13] F. Ye and K. Chakrabarty, “TSV Open Defects in 3D Integrated Circuits: Characterization, Test, and Optimal Spare Allocation,” Proc. of Design Automation Conf., pp. 10240-1030, June 2012.
[14] J. Carretero, X. Vera, P. Chaparro, and J. Abella, “Microarchitectural Online Testing for Failure Detection in Memory Order Buffer,” IEEE Trans. on Computers, Vol. 59, No. 5, pp. 623-637, 2010.
[15] Y. Li, Y. M. Kim, E. Mintarno, D. S. Gardner, and S. Mitra, “Overcoming Early-Life Failure and Aging for Robust Systems,” IEEE Design & Test of Computers, Vol. 26, No. 6, pp. 28-39, 2009.
[16] T. H. Kim, R. Persaud, and C. H. Kim. “Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits,” IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, pp. 874-880, 2008.
[17] X. Wang, L. Winemberg, D. Su, D. Tran, S. George, N. Ahmed, S. Palosh, A. Dobin, and M. Tehranipoor, "Aging Adaption in Integrated Circuits Using a Novel Built-In Sensor," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 109-121, Vol. 34, No. 1, 2015.
[18] S.-Y. Huang, H.-X. Li, Z.-F. Zeng, K.-H. Tsai, and W.-T. Cheng, "On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs," Proc. of Asian Test Symp., pp. 162-167, Nov. 2014.
[19] M.-T. Tsai, S.-Y. Huang, K.-H. (Hans) Tsai, and W.-T. Cheng, "Monitoring the Delay of Long Interconnects via Distributed TDC," Proc. of IEEE Int'l Test Conf., Oct. 2015.
[20] M. Sadi, L. Winemberg, and M. Tehranipoor, “A Robust Digital Sensor IP and Sensor Insertion Flow for In-Situ Path Timing Slack Monitoring in SoCs,” Proc. of IEEE VLSI Test Symp. (VTS), pp. 1-6, April 2015.
[21] “CIC Reference Flow for Cell-based IC Design,” Chip Implementation Center, Taiwan, Document no. CIC-DSD-RD-08-01, 2008.
[22] D. Ernst et al, “Razor: a low-power pipeline based on circuit-level timing speculation,” Proc. of 36th Int'l IEEE Symp. on Microarchitecture (MICRO-36), pp. 7-18, December 2003.
[23] J. Park and J. A. Abraham, “An aging-aware flip-flop design based on accurate, run-time failure prediction,” Proc. of IEEE VLSI Test Symp. (VTS), pp. 294-299, April 2012.
[24] http://www.synopsys.com/COMMUNITY/UNIVERSITYPROGRAM/
(此全文限內部瀏覽)
電子全文
摘要
 
 
 
 
第一頁 上一頁 下一頁 最後一頁 top
* *