本論文提出一個以標準元件庫細胞為基礎的時間量化器電路架構及其電路自動產生軟體來自動產生符合需求的時間量化器電路。由於製程檔所提供的數據為近似值，再加上結果會隨著自動佈局階段擺放位置與繞線不同而產生變異，使得脈衝萎縮模組的量化結果與預期不太相符。為了解決這個問題，微調元件的解析度都會預先做電晶體層的模擬驗證，由此可整理出在台積電90nm製程下適合縮減脈衝寬度架構之微調元件。額外加上一個可調控萎縮量的粗調電路能使整個架構更穩定不受製程變異影響。最後解碼器的輸出結果會由內差法轉變到時域上的值讓後端使用更直觀方便。內差過程中會利用多次取樣的方法來降低時脈訊號抖動所造成的誤差。我們提出的系統能在數分鐘內產生出符合使用者需求的時間量化器，並節省設計流程所要消耗的資源與時間成本。該時間量化器電路編譯軟體能支援1ns至8ns的輸入範圍，並有數種微調元件可供選擇，大幅增加使用的彈性。

This thesis proposes a cell-based Time-to-Digital Converter (TDC) architecture and its compiler, which can generate cell-based TDC circuits automatically. Because the values from data book are approximations and the result could vary from different routing conditions in APR stage, the quantized outcome of shrinking line may not meet the expectations. In order to solve this problem, the resolution of fine-shrinking cells are pre-confirmed in transistor level simulation. It also reorganizes the components that are suitable for pulse-shrinking architecture in TSMC 90nm CMOS process technology. A coarse block with an adjustable shrinking amount is used to prevent the side effects of the process variation. The output digital code is turned into an absolute value by a built-in interpolation scheme to make the back-end operation intuitively. The error caused by clock jitter during the interpolation is reduced by a multi-sample methodology. The proposed system can generate a TDC circuit in minutes with user’s specification. It saves not only time but effort in the design flow. The result from simulation shows that the proposed TDC compiler can support input range from 1ns to 8ns with many choosable shrinking cells and different target ranges. These features increase the flexibility of TDC compiler greatly.

致謝 i
Abstract ii
摘要 iii
Content iv
List of Figures vi
List of Tables viii
Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 2
1.3 Organization of Thesis 2
Chapter 2 Related Work 3
2.1 Quantize Technique 3
2.1.1 Counter-based Approaches 3
2.1.2 Delay-line-based (DL-based) Approaches 4
2.1.3 Pulse-shrinking Approaches 5
Chapter 3 Architecture and Operation of TDC 7
3.1 Architecture of proposed TDC 7
3.1.1 Fine Block 8
3.1.2 Coarse Block 10
3.1.3 Self-Controller 12
3.1.4 Control Unit 13
3.2 Operating Flow 14
3.2.1 Range Calibration 15
3.2.2 Pulse Calibration 17
3.2.3 Calculated Preparation 18
3.2.4 Pulse-Shrinking 19
3.2.5 Interpolation 19
Chapter 4 Architecture and Methodology of Compiler 21
4.1 Basic Constraints 21
4.2 Graphical User Interface (GUI) and Operation 22
4.3 Shrinking Cell Selected Methodology 24
4.4 Variation Tolerance Methodology 27
4.4.1 Variation Tolerance in Pulse Shrinking Amount 28
4.4.2 Variation Tolerance in Propagation Delay 30
4.5 Jitter Exclusion Methodology 32
4.6 Placement Methodology 34
Chapter 5 Experimental Results 36
5.1 Verification of TDC with Typical Case 36
5.2 Error Comparison with Different Shrinking Cells 40
5.3 Verification of TDC with Various Specifications 41
Chapter 6 Conclusion 46
References 47

[1] K. Karadamoglou, N. P. Paschalidis, E. Sarris, N. Stamatopoulos, G. Kottaras, and V. Paschalidis, “An 11-bit High-Resolution and Adjustable-Range CMOS Time-to-Digital Converter for Space Science Instruments,” in Proc. IEEE Journal of Solid-State Circuits, Vol. 39, pp. 214-222, Jan. 2004.
[2] Y.-C. Chang, S.-Y. Huang, C.-W. Tzeng, and Y. Yao, “A fully cell-based design for timing measurement of memory,” in Proc. IEEE ITC, Nov. 2011.
[3] C.-H. Hsu, S.-Y. Huang, D.-M. Kwai, and Y.-F. Chou, “Worst-Case IR-Drop Monitoring with 1GHz Sampling Rate,” in Proc. IEEE VLSI-DAT, Apr. 2013
[4] Stephan Henzler. (2010). Time-to-Digital Converters. Springer Netherlands
[5] C.-W. Tzeng, S.-Y. Huang, P.-Y. Chao, and R.-T. Ding, "Parameterized All-Digital PLL Architecture and Its Compiler to Support Easy Process Migration," IEEE Trans. on VLSI Systems (TVLSI), Vol. 22, No. 3, pp. 621-630, Mar. 2014.
[6] P.-C. Huang and S.-Y. Huang, “A Compiler Methodology for Delay Locked Loop Using Only Standard Cells,” Electrical Engineering Department National Tsing Hua University, Taiwan.
[7] N. Kurosawa et al., “Sampling clock jitter effects in digital-to-analog converters,” Measurement, vol. 31, no. 3, pp. 187–199, Apr. 2002.
[8] Wang Yonggang, Liu Chong, and Zhu Wensong, “Two Novel Designs of Multi-Phase Clocked Ultra-High Speed Time Counter on FPGA for TDC Implementation,” in Proc. IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2013.
[9] H.-Y. Huang, J.-C. Liu, P.-Y. Lee, K.-Y. Chen, J.-S. Chen, K.-H. Cheng, T.-H. Huang, C.-H. Luo and J.-C. Chiou, “PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing,” in Proc. IEEE International Sym. On Des. And Diag. of Elect. Circuits & Syst. (DDECS), 2015.
[10] M. Abdelmejeed, R. Guindi and M. Abdel-Moneum, ”A Novel High Throughput High Resolution Two-Stage Oscillator-Based TDC,” IEEE SoC Design Conference (ISOCC), Nov. 2013.
[11] Yanfeng Li, Ni Xu, Woogeun Rhee, and Zhihua Wang, “A 2.5GHz ADPLL with PVT-Insensitive ΔΣ Dithered Time-to-Digital Conversion by Utilizing an ADDLL,” IEEE International Symposium on Circuits and Systems (ISCAS), 2014.
[12] Vineet Sharma, Nupur Jain, Biswajit Mishra, “Fully-Digital Time based ADC/TDC in 0.18µm CMOS,” IEEE International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA), 2016.
[13] Minjae Lee and Asad A. Abidi, “A 9b, 1.25ps Resolution Coarse-Fine Time-to-Digital Converter in 90nm CMOS that Amplifies a Time Residue,” in Proc. IEEE VLSI Circuits, Jun. 2007.
[14] S. Henzler, S. Koeppe, W. Kamp, H. Mulatz, and D. S.-Landsiedel, “90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive Interpolation Time-to-Digital Converter with On-Chip Characterization,” IEEE International Solid-State Circuits Conference – Digest of Technical Papers (ISSCC), Feb. 2008
[15] Jianjun Yu, Fa Foster Dai, and Richard C. Jaeger, “A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 m CMOS Technology,” in proc. IEEE Journal of Solid-State Circuits, vol. 45, pp. 830-842, Mar. 2010.
[16] Poki Chen, Shen-Iuan Liu, and Jingshown Wu, “A CMOS Pulse-Shrinking Delay Element For Time Interval Measurement,” in Proc. Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, Sep. 2000.
[17] Yue Liu, Ulrich Vollenbruch, Yangjian Chen, Christian Wicpalek, Linus Maurer, Zdravko Boos, and Robert Weigel, “A 6ps Resolution Pulse Shrinking Time-to-Digital Converter as Phase Detector in Multi-Mode Transceiver,” in Proc. IEEE Radio and Wireless Symposium, pp. 163-166, 2008.
[18] Yue Liu, Ulrich Vollenbruch, Yangjian Chen, Christian Wicpalek, Linus Maurer, Zdravko Boos, and Robert Weigel, “Multi-stage Pulse Shrinking Time-to-Digital Converter for Time Interval Measurements,” in Proc. European Microwave Integrated Circuit Conference (EuMIC), pp. 267-270, 2007
[19] Chun-Chi Chen, Shih-Hao Lin, and Chorng-Sii Hwang, “An Area-Efficient CMOS Time-to-Digital Converter Based on Pulse-Shrinking Scheme,” in Proc. IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 61, no. 3, Mar. 2014.
[20] G. K. Dehng, J. M. Hsu, C. Y. Yang, and S. I. Liu, “Clock-deskew buffer using a SAR-controlled delay-locked loop,” IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1128–1136, Aug. 2000.
[21] K.-S. Kim, Y.-H. Kim, W. Yu, and W.-H. Cho, “A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 1009-1017, Apr. 2013.
[22] P. Chen, Y.-Y. Hsiao, and Y.-S. Chung, “A High Resolution FPGA TDC Converter with 2.5 ps Bin Size and -3.79~6.53 LSB Integral Nonlinearity, ” IEEE international Conference on Intelligent Green Building and Smart Grid (IGBSG), 2016.