在使用先進製程製造電路的過程中，物理性的缺陷可能會發生在任何一個製造階段，進而造成最終產品的損害，而隨著製程技術的進步，電路內的密度以及複雜度也會隨之提高，這些缺陷也越來越難以被檢測出。在現在廣泛所使用的閘位準測試形樣中，例如：由常規的自動測試形樣產生系統所產生的固定型故障形樣；對於發生在閘內部的缺陷會難以建立模型，進而去做檢測，所以單元認知測試就被提出，用以檢測這種之前無法有效處理的缺陷。單元認知測試已被證實對於工業上以互補金屬氧化物半導體為基底的設計，能夠有效的降低產品的缺陷水準，但在單元認知測試的過程中，因為需要對每個缺陷單元做詳細的電晶體位準模擬，所以會導致整個過程非常的耗時，這主要的原因是在寄生參數提取後的電路中，所有的寄生電容和電阻，都會被視為是個別且潛在的缺陷，造成了整個潛在的缺陷集會相當的龐大。為了要能夠縮減缺陷集，我們在判斷每個單元內潛在的缺陷時，會將實際單元的電路布局列入考量，這能夠有效的排除其中一些多餘或不必要的缺陷，進而大幅減少缺陷的數量，並且能夠縮短模擬缺陷電路行為所需的時間。在我們所提出的方法中，我們會根據實際單元的布局來建立缺陷模型，這些缺陷模型會更加接近在真實的電路布局中所可能發生的物理性缺陷，同時，潛在缺陷的總數在與單元認知測試的比較下，也有明顯的下降。我們使用工業用的180奈米以及350奈米級金屬氧化物半導體標準單元庫來驗證我們所提出的方法，在實驗的結果中，缺陷的個數減少到了單元認知測試的20%或甚至更低，同時也代表了我們可以大幅減少模擬所需的時間。

Because of the high complexity and density of modern CMOS circuits due to the continuous technology advancement, it is more and more difficult to detect physical defects, which can occur during any step of the fabrication process, on a modern CMOS chip using advanced technology. Therefore, the cell-aware test (CAT) methodology was previously proposed to target the cell-internal defects that cannot be easily detected by the gate-level stuck-at fault (SAF) patterns generated by the conventional ATPG tools. It was shown to reduce the defect level on industrial CMOS-based designs, with the help of detailed defect injected transistor-level circuit simulation and defect-enhanced SAF ATPG. However, the detailed transistor-level circuit simulation has been considered an issue in CAT, as it is very time consuming. The problem mainly lies in that all parasitic capacitors and resistors extracted from cell layout are considered as defect targets, so the defect set is large. To reduce the number of the defect set, and therefore the circuit simulation time, we take layout into consideration when we construct the defect set for each cell, effectively removing the redundant or unnecessary defects and therefore reducing the circuit simulation time dramatically. We propose a generalized approach that can be used to build the fault models based on the cell layout, where the generated faults are closer to the realistic physical defects on the layout, so the number of faults can be significantly reduced. The proposed method is verified by commercial 180nm and 350nm CMOS standard cell library, and the circuit simulation time is reduced to about only 20% or even lower as in comparison with the original CAT methodology.

List of Figures iv
List of Tables vi
Chapter 1 Introduction 1
1.1 Detecting Defects within Circuits 1
1.2 Testing for Cell-Internal Defects 3
1.3 Objective of This Work 5
1.4 Organization of The Thesis 6
Chapter 2 Cell-Aware Test 7
2.1 The CAT Methodology 7
2.2 Summary of CAT 14
2.3 Issues and Possible Improvements 14
Chapter 3 Layout-Oriented Defect Set Generation 17
3.1 Overview 17
3.2 Layout Identification 18
3.3 Fault Injection 31
Chapter 4 Experimental Results 35
4.1 Results for 180nm Library Cells 36
4.2 Results for 350nm Library Cells 39
Chapter 5 Conclusions and Future Work 42
5.1 Conclusions 42
5.2 Future Work 43
Bibliography 45

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