車用電子、手持式電子產品、醫療電子等大量電子產品對下世代非揮發性記憶體的市場需求愈來愈大，尤其是大容量、低成本、低功率消耗和高效能的記憶體。目前主流的非揮發性記憶體為快閃記憶體(Flash Memory)，然而其在寫入時需要高電壓且寫入速度速度慢以及無法隨機讀取的情況下，開發新型的非揮發性記憶體才能夠繼續符合市場的需求。新世代記憶體中，電阻式記憶體(ReRAM)是相當具有潛力的，其特色為低寫入能耗、小面積、以及具有邏輯製成相容性，可大大地降低製作成本。
隨著元件的微縮，趨勢顯示ReRAM的阻值愈來愈高。寫入時間和阻值分布愈來愈廣的情況下，也造成高阻態和低阻態之間的阻值比(R-ratio, RH/RL)縮小。
因此ReRAM記憶體會面臨到兩個主要的問題：
1. R-ratio縮小導致讀取的感測範圍縮減。
2. 寫入時間分布廣所造成的寫入能耗浪費及多餘的電壓壓迫。
在此，我們提出了末端位元電阻值調整寫入(bottom-controlled tail-bit resistance-tuning write, BCRTW) 機制來解決上述問題。
我們所提出的BCRTW 機制是多步驟的寫入機制，其可以利用多種方法來節省寫入能耗，包含了在第一步驟降低直流電流、去除了常開式運算放大器的設計以及寫入終止機制。我們利用的寫入終止機制來解決多於電壓壓迫問題，最後電阻值調整的觀念更可放大R-ratio。
我們以台積電65奈米邏輯製程實作2Mb Contact-ReRAM記憶體晶片，在快速轉態記憶胞及慢速轉態記憶胞的實作上，BCRTW的功能都獲得了驗證。

The marketing requirements of next generation non-volatile memories for automobile electronics, handheld consumer electronics, medical electronics and lots of electronic products become larger and larger; especially we need large capacity, low cost, low power and high performance memory. Flash memory is the mainstream embedded non-volatile memory; however, the write operation needs high voltage and lots of programming time, and we cannot randomly access the memory during read operation. Thus, developing new nonvolatile memories is necessary to meet the marketing requirement. Among these emerging nonvolatile memories, Resistive Random Access Memory (ReRAM) is one of the most promising candidates. It has many attractive characteristics such as low write energy, small area, and logic-process compatibility which can lower the manufacturing cost.
As devices shrink, the trend shows that ReRAM has higher cell resistance (R) and wider distribution in write time and R, which reduces the R-ratio (RH/RL) between the high resistance state (HRS, RH) and low resistance state (LRS, RL).
Thus, ReRAM memory macro designs suffer two major problems：
1. Small sensing margin due to the small R-ratio
2. Wide SET/RESET time distribution cause the wasted write energy and over-stress
time
Here, we propose bottom-controlled tail-bit resistance-tuning write (BCRTW) scheme to solve these problems.
Proposed BCRTW scheme is a multiple steps write scheme, and it can save the write energy in various ways, including lowering DC current in step-1, eliminating always-on OP design and self-adaptive termination scheme. The over-stress problem can be well solved by the SET/RESET termination, which benefits the ReRAM device. Finally, the resistance-tuning concept can enlarge the R-ratio.
We fabricated a 65nm 2Mb Contact-ReRAM memory macro with TSMC logic-compatible process. The function of BCRTW scheme has been verified for fast-switch cell and slow-switch cell.

摘要 ii
Abstract iii
Contents vii
List of Figures ix
List of Tables xi
Chapter 1 Introduction 1
1.1 The Memory Landscape 1
1.2 Challenges of Flash Memory 3
1.3 Emerging Non-Volatile Memories 5
Chapter 2 Characteristic of Contact-ReRAM 9
2.1 Structure of Contact-ReRAM 9
2.2 Distribution of Contact-ReRAM 11
2.3 Read Operation 13
2.4 Write Operation 15
Chapter 3 Design Challenges of ReRAM 17
3.1 Design Challenge of ReRAM Read 17
3.2 Design Challenge of ReRAM Write 22
3.3 Previous Arts 24
Chapter 4 Proposed Circuits Schemes 27
4.1 Bottom-controlled tail-bit Resistance-tuning Write (BCRTW) scheme 27
4.1.1 Concept and structure of BCRTW scheme 28
4.1.2 Operation of BCRTW scheme 29
4.2 Analysis and Comparisons 34
4.2.1 Analysis of the choice of VGWD 35
4.2.2 Write Energy Comparisons 36
4.2.3 Comparison with Other Previous Works 38
Chapter 5 Measurement Result and Conclusion 39
5.1 Macro Implementation 39
5.2 Design for Test 41
5.3 Measurement Result 42
5.4 Conclusion and Future Works 44
Reference 48

[1] C. Villa et al., "A 125 MHz burst-mode flexible read-while-write 256 Mbit 2b/c 1.8V NOR flash memory," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 52-584, Feb. 2005.
[2] M. F. Chang and S. J. Shen, "A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme," IEEE Journal of Solid-State Circuits, vol. 44, no. 3, pp. 987-994, March 2009.
[3] J. Javanifard et al., "A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 424-624, Feb. 2008.
[4] C. Gerardi et al., "Performance and reliability of a 4Mb Si nanocrystal NOR Flash memory with optimized 1T memory cells," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 1-4, Dec. 2008.
[5] T. Ogura et al., "A fast rewritable 90nm 512Mb NOR “B4-Flash” memory with 8F2 cell size," Symposium on VLSI Circuits Dig. Tech. Papers, pp. 198-199, June 2011.
[6] H. T. Lue et al., "A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device," Symposium on VLSI Technology Dig. Tech. Papers, pp. 131-132, June 2010.
[7] C. P. Chen et al., "A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)," Symposium on VLSI Technology Dig. Tech. Papers, pp. 91-92, June 2012.
[8] H. T. Lue et al., "A novel bit alterable 3D NAND flash using junction-free p-channel device with band-to-band tunneling induced hot-electron programming," Symposium on VLSI Technology Dig. Tech. Papers, pp. 152-153, June 2013.
[9] K. T. Park et al., "Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 334-335, Feb. 2014.
[10] R. Cernea et al., "A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 420-624, Feb. 2008.
[11] Choong-Ho Lee et al., "A highly manufacturable integration technology for 27nm 2 and 3bit/cell NAND flash memory," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 5.1.1-5.1.4, Dec. 2010.
[12] Y. Koh, "NAND Flash Scaling Beyond 20nm," IEEE International Memory Workshop, pp. 1-3, May 2009.
[13] K. Prall, "Scaling Non-Volatile Memory Below 30nm,"IEEE Non-Volatile Semiconductor Memory Workshop, Monterey, pp. 5-10, 2007.
[14] S. Lee, "Scaling Challenges in NAND Flash Device toward 10nm Technology," IEEE International Memory Workshop, pp. 1-4, May 2012.
[15] K. Takeuchi, "Scaling challenges of NAND flash memory and hybrid memory system with storage class memory & NAND flash memory," IEEE Custom Integrated Circuits Conference, pp. 1-6, 2013.
[16] YunSeung Shin, "Non-volatile memory technologies for beyond 2010," Symposium on VLSI Circuits Dig. Tech. Papers, pp. 156-159, June 2005.
[17] J.-P. Colinge, et al., "Physics of Semiconductior Devices," Kluwer Academic Publishers, 2002.
[18] R. Takemura et al., "A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme," IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 869-879, April 2010.
[19] J. J. Nahas et al., "A 180 Kbit Embeddable MRAM Memory Module," IEEE Journal of Solid-State Circuits, vol. 43, no. 8, pp. 1826-1834, Aug. 2008.
[20] D. Gogl et al., "A 16-Mb MRAM featuring bootstrapped write drivers," IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 902-908, April 2005.
[21] D. Halupka et al., "Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 256-257, Feb. 2010.
[22] K. C. Chun, H. Zhao, J. D. Harms, T. H. Kim, J. P. Wang and C. H. Kim, "A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory," IEEE Journal of Solid-State Circuits, vol. 48, no. 2, pp. 598-610, Feb. 2013.
[23] G. De Sandre et al., "A 90nm 4Mb embedded phase-change memory with 1.2V 12ns read access time and 1MB/s write throughput," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 268-269, Feb. 2010.
[24] K. J. Lee et al., "A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 472-616, Feb. 2007.
[25] F. Bedeschi et al., "A Multi-Level-Cell Bipolar-Selected Phase-Change Memory," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 428-625, Feb. 2008.
[26] F. Bedeschi et al., "A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage," IEEE Journal of Solid-State Circuits, vol. 44, no. 1, pp. 217-227, Jan. 2009.
[27] H. Y. Cheng et al., "A high performance phase change memory with fast switching speed and high temperature retention by engineering the GexSbyTez phase change material," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 3.4.1-3.4.4, Dec. 2011.
[28] J. Y. Wu et al., "A low power phase change memory using thermally confined TaN/TiN bottom electrode," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 3.2.1-3.2.4, Dec. 2011.
[29] T. Morikawa et al., "A low power phase change memory using low thermal conductive doped-Ge2Sb2Te 5 with nano-crystalline structure," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 31.4.1-31.4.4, Dec. 2012.
[30] H. Shiga et al., "A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 464-465, Feb. 2009
[31] D. Takashima et al., "A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 262-263, Feb. 2010.
[32] M. Qazi et al., "A low-voltage 1Mb FeRAM in 0.13μm CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOS," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 208-210, Feb. 2011.
[33] Y. S. Chen et al., "Forming-free HfO2 bipolar RRAM device with improved endurance and high speed operation," IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), pp. 37-38, April 2009.
[34] H. Y. Lee et al., "Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 1-4, Dec. 2008.
[35] Y. S. Chen et al., "Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 1-4, Dec. 2009.
[36] S. S. Sheu et al., "A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme," Symposium on VLSI Circuits Dig. Tech. Papers, pp. 82-83, June 2009.
[37] Y. H. Tseng et al., "High density and ultra small cell size of Contact ReRAM (CR-RAM) in 90nm CMOS logic technology and circuits," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 1-4, Dec. 2009.
[38] C. H. Cheng, A. Chin and F. S. Yeh, "Novel Ultra-low power RRAM with good endurance and retention," Symposium on VLSI Technology Dig. Tech. Papers, pp. 85-86, June 2010.
[39] S. S. Sheu et al., "A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 200-202, Feb. 2011.
[40] R. Meyer et al., "Oxide dual-layer memory element for scalable non-volatile cross-point memory technology," Non-Volatile Memory Technology Symposium (NVMTS), pp. 1-5, 2008.
[41] M. F. Chang et al., "A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 434-436, Feb. 2012.
[42] T. Y. Liu et al., "A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 210-211, Feb. 2013.
[43] W. C. Shen et al., "High-K metal gate contact RRAM (CRRAM) in pure 28nm CMOS logic process," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 31.6.1-31.6.4, Dec. 2012.
[44] http://www.businesskorea.co.kr/article/1687/local-market-saturation-korea%E2%80%99s-smartphone-market-forecast-negative-growth-year.
[45] http://www.appguru.com.tw/appguru/blog/20839/ipad-mini-2-has-finally-started-selling-the-first-wave-of-pull-national-price-comparison-and.
[46] http://www.cbronline.com/news/mobile-and-tablets/mobile-smart-wearable-devices-revenue-to-reach-19bn-by-2018-161013.
[47] http://medicaldesign.com/electronics/smart-baby-monitor-tracks-rest-and-well-being.
[48] http://www.cvel.clemson.edu/auto/systems/auto-systems.html.
[49] http://bensontao.wordpress.com/2013/10/06/vivante-internet-of-things/.
[50] N. Xu et al., "A unified physical model of switching behavior in oxide-based RRAM," Symposium on VLSI Technology Dig. Tech. Papers, pp. 100-101, June 2008.
[51] C. Ho et al., "A Highly Reliable Self-Aligned Graded Oxide WOx Resistance Memory: Conduction Mechanisms and Reliability," Symposium on VLSI Technology Dig. Tech. Papers, pp. 228-229, June 2007.
[52] M. J. Lee et al., "2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 771-774. Dec. 2007.
[53] B. Gao et al., "Oxide-based RRAM switching mechanism: A new ion-transport-recombination model," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 1-4, Dec. 2008.
[54] C. H. Wang et al., "Three-dimensional 4F2 ReRAM cell with CMOS logic compatible process," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 29.6.1-29.6.4, Dec. 2010.
[55] G. Bersuker et al., "Metal oxide RRAM switching mechanism based on conductive filament microscopic properties," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 19.6.1-19.6.4, Dec. 2010.
[56] J. Lee et al., "Diode-less nano-scale ZrOx/HfOx RRAM device with excellent switching uniformity and reliability for high-density cross-point memory applications," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 19.5.1-19.5.4, Dec. 2010.
[57] C. J. Chevallier et al., "A 0.13µm 64Mb multi-layered conductive metal-oxide memory," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 260-261, Feb. 2010.
[58] K. Aratani et al., "A Novel Resistance Memory with High Scalability and Nanosecond Switching," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 783-786, Dec. 2007.
[59] W. Otsuka et al., "A 4Mb conductive-bridge resistive memory with 2.3GB/s read-throughput and 216MB/s program-throughput," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 210-211, Feb. 2011.
[60] C. Cagli et al., "Evidence for threshold switching in the set process of NiO-based RRAM and physical modeling for set, reset, retention and disturb prediction," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 1-4, Dec. 2008.
[61] Y. H. Tseng et al., "Electron trapping effect on the switching behavior of contact RRAM devices through random telegraph noise analysis," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 28.5.1-28.5.4, Dec. 2010.
[62] Byoungil Lee and H. S. P. Wong, "NiO resistance change memory with a novel structure for 3D integration and improved confinement of conduction path," Symposium on VLSI Technology Dig. Tech. Papers, pp. 28-29, June 2009.
[63] H. Y. Chen, S. Yu, B. Gao, P. Huang, J. Kang and H. S. P. Wong, "HfOx based vertical resistive random access memory for cost-effective 3D cross-point architecture without cell selector," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 20.7.1-20.7.4, Dec. 2012.
[64] Y. B. Kim et al., "Bi-layered RRAM with unlimited endurance and extremely uniform switching," Symposium on VLSI Technology Dig. Tech. Papers, pp. 52-53, June 2011.
[65] Z. Wei et al., "Highly reliable TaOx ReRAM and direct evidence of redox reaction mechanism," IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 1-4, Dec. 2008.
[66] M. F. Chang et al., "An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 206-208, Feb. 2011.
[67] M. Jefremow et al., "Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 216-217, Feb. 2013.
[68] M. Qazi et al., "A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 350-351, Feb. 2010.
[69] X. Y. Xue et al., "A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction," Symposium on VLSI Circuits Dig. Tech. Papers, pp. 42-43, June 2012.
[70] M. F. Chang et al., "Area-efficient embedded RRAM macros with sub-5ns random-read-access-time using logic-process parasitic-BJT-switch (0T1R) Cell and read-disturb-free temperature-aware current-mode read scheme," Symposium on VLSI Circuits Dig. Tech. Papers, pp. C112-C113, June 2013.
[71] T. Kono et al., "40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 212-213, Feb. 2013.
[72] A. Kawahara et al., "An 8Mb multi-layered cross-point ReRAM macro with 443MB/s write throughput," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 432-434, Feb. 2012.
[73] M. F. Chang et al., "Embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 332-333, Feb. 2014.
[74] B. Giridhar et al., "A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 242-243, Feb. 2014.
[75] C. C. Lin et al., "A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14x improvement in wordlength-energyefficiency-density product using 2.5T1R cell," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 136-137, Feb. 2016