此篇論文闡述一個有效率的機率紀錄器之協同低密度奇偶檢查解碼器，此解碼器結合一個位元轉換(bit-flipping)解碼器，用來降低解碼時間。論文中提出一種以VN為單位的機率紀錄器，不同於以往的隨機解碼器中的機率紀錄器，此機率紀錄器使用C2V信息，根據類似於APP值計算的公式，從C2V信息中得出一個可被機率紀錄器紀錄的值，使解碼器擁有與MSA相當的解碼能力，本論文提出的以C2V信息為值之機率紀錄器可使電路的路徑縮短，進而使解碼器運作在高頻的電路上，增加解碼器的吞吐量。本論文提出不同的晶片面積節省方法，省略隨機解碼器的共同電路，本論文提出的以C2V為值之機率紀錄器能與其他架構結合，更進一步減少面積，降低擁有機率紀錄器之VN的複雜度。為了解決較長的解碼時間，本論文提出隨機解碼器與位元轉換解碼器協同解碼，在特定條件下啟動位元轉換解碼器，加速解碼過程的收斂，使隨機解碼器在沒有降低解碼能力的情況下減少解碼的時間，雖然增加些許的面積，但能增加不少解碼器的吞吐量。本篇提出的方法使用(2048, 1723)低密度奇偶檢查的解碼器來應證，在90製程實作下，解碼器有1450K的邏輯數，4.12 mm^2的實際面積，在頻率為749 MHz下有39.3 Gbps的吞吐量，與我們所知的隨機解碼器相比，本篇提出的架構有最好的解碼能力和標準化後的單位面積吞吐量。

This thesis presents an efficient collaborated stochastic low-density parity-check (LDPC) decoder, where a bit-flipping (BF) based collaborative decoder is used to achieve less decoding cycles without degradation in bit-error-rate (BER) performance. A node-wise probability tracer is adapted at each variable node (VN) in order to achieve a BER performance comparable to the normalized min-sum algorithm, where the check-to-variable (C2V) messages rather than the variable-to-check (V2C) messages adopted in the previous stochastic decoders are used as inputs. The complexity of VN units is greatly reduced by sharing common units used in the generation of V2C messages and the probability tracer. The C2V-based probability tracer enables the design of a decoder with short critical path. The proposed methods are demonstrated by implementing a (2048, 1723) decoder. Fabricated in a 90nm process, the decoder integrates 1460K logic gates in 4.12 mm^2 and achieves a throughput of 39.3 Gbps at a clock of 749 MHz. To the best of our knowledge, the proposed decoder achieves the best BER performance and normalized throughput-to-area ratio among the stochastic decoders reported in the open literatures.

Abstract I
中文摘要 I
第一章 簡介 1
第二章 隨機低密度機偶檢查解碼器的回顧 5
第三章 高效率低面積機率紀錄器及快速收斂協同解碼器 16
第四章 實作與測試結果 36
第五章 結論 48

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