隨著製程技術不斷的演進，元件的尺寸越來越小。複雜度也隨著摩爾定律不斷提高，造成製程所產生的缺陷變得更難以檢測。而沒有被檢測出的缺陷元件，會造成非常嚴重的退貨問題，使得產品缺陷水準急遽飆升。這些缺陷並不能被一般所以使用的自動測試形樣產生系統，所產生的形樣檢測出錯誤。傳統的測試方法也沒有針對閘內的缺陷建立模型。為了能夠有效的降低缺陷水準元件認知測試的方法被提出，並特別針對元件內的缺陷建立模型。然而，現今還沒有辦法證明元件認知測試能夠有效的降低缺陷水準。也就是說，如何達到更高的缺陷的覆蓋率仍然是很重要的問題。另一個傳統元件認知測試待改善的問題是，由於過程中，需要對每個缺陷元件做詳盡的電晶體位準模擬，所以會耗費相當長的時間。此部分已由我們實驗室的成員劉軒瑋，根據實際元件電路的布局所提出新的方法，來排除多餘、不必要的缺陷以縮減缺陷集。
而本篇論文，我們主要針對的問題是如何有效提升缺陷覆蓋率，並對於所有32個元件的短路及開路缺陷做模擬。使用的元件庫為工業用的180奈米級金屬氧化物半導體標準元件庫。並且，使用上述的「針對加速元件認知測試電路模擬之實體布局缺陷集縮減研究」中的缺陷集來做模擬；而此方法的缺陷覆蓋率和傳統的元件認知測試是相當的。我們對每個缺陷集中缺陷做電晶體位準模擬，並額外提供漏電流的資訊。因此，能夠了解在元件認知測試中，哪些缺陷是無法被邏輯準位測試所檢測出的。我們將各元件對於「針對加速元件認知測試電路模擬之實體布局缺陷集縮減研究」的方法，以及本篇所提出的「引進漏電流於缺陷辭典以強化元件認知測試」的方法做缺陷覆蓋率的比較。「針對加速元件認知測試電路模擬之實體布局缺陷集縮減研究」的方法其平均缺陷的覆蓋率為93%，而藉由本篇論文引進漏電流的方法可提高7%的缺陷覆蓋率。對於32個元件都達到100%的缺陷覆蓋率。最後，我們也對於此缺陷集分別做固定型故障形樣及轉態延遲障礙形樣的缺陷的覆蓋率比較。其中形樣均為工業用自動測試形樣產生系統所產生。此缺陷集的固定型故障形樣的缺陷覆蓋率為89%。而藉由延遲障礙形樣可而外提升4%的缺陷覆蓋率，而達到上述的平均93%缺陷覆蓋率。

As the semiconductor fabrication technology continues to advance and device feature size and supply voltage are being scaled down following Moore’s Law, it is getting harder and harder to tackle with all kinds of variation and uncertainty. As a result, the number of undetected defects that are contained in shipped products using advanced technologies rises rapidly, driving their Defect Level (DL) up. Those defects apparently are not covered by conventional Stuck-At Fault (SAF) and Transition Fault (TF) models, which are typically used by commercial products to guarantee the product quality before shipping. A high DL means that a high number of defective devices pass the final test and are shipped to the customer, which will eventually cause escalating overhead (extra cost) due to unacceptable system product quality. In order to reduce the DL, there are many methodologies proposed recently. The Cell-Aware Test (CAT) methodology was proposed to target the cell-internal open and short defects which are more realistic than the conventional gate-level test flow. However, so far it has not been well proved that CAT can reduce DL effectively and efficiently for most advanced products, i.e., higher defect coverage is still of high priority in the agenda. Another issue is that the original CAT approach is very time-consuming. This issue has been addressed recently by one of our group members, Hsuan-Wei Liu, who has proposed a novel layout-based method to reduce the defect set by removing redundant or unnecessary defects [5].
In this work, we stress the issue of improving the defect coverage. To demonstrate our approach, we simulated 32 standard cells from a typical commercial 180nm CMOS cell library, for both the open and short defects. The defect set that we use is from the enhanced CAT method based on cell layout [5]. By SPICE simulation for each and every defect in the set, we obtain the extra information for the leakage current, so we are able to identify those defects that cannot be detected by the voltage (logic) test in the original CAT approach. Note that the layout-based CAT has a comparable defect coverage with the original CAT, so in our work we compare the defect coverage at the cell level between the layout-based CAT method [5] and the proposed leakage-current enhanced CAT, with a commercial ATPG tool. The layout-based CAT with SAF and TF tests can detect 93% of the open and short defects as defined in the reduced defect set. With the leakage-current enhanced CAT, the defect coverage can increase by 7% on average, and reach 100% in all cases (for all cells).
Finally, we also calculate the defect coverage by the SAF and TF patterns, respectively, with a commercial ATPG tool for the layout-based CAT [5]. The defect coverage by the SAF patterns is 89% on average, i.e., about 11% of the defects cannot be covered by the SAF patterns. We then calculate the extra defect coverage that can be achieved by the TF patterns, which is 4%, so the total defect coverage is 93% on average as mentioned above.

Abstract i
Contents iii
List of Figures v
List of Tables viii
Chapter 1 Introduction 1
1.1 Cell-Aware Test 1
1.2 Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in CAT 8
1.3 Objective 12
1.4 Thesis Organization 14
Chapter 2 Analog Fault Simulation 15
2.1 Test Generation 15
2.2 Voltage Threshold 16
2.3 Initial Setting of Open Defect 17
2.4 Time Cost 18
Chapter 3 Defect Dictionary 19
3.1 Short Defects 20
3.2 Open Defects with Low Initial Value and High Initial Value 24
Chapter 4 Defect Coverage Improvement 29
4.1 Defect Coverage Calculation 30
4.2 Improved Defect Coverage 36
Chapter 5 Conclusions and Future Work 41
5.1 Conclusions 41
5.2 Future Work 42
Bibliography 43
Appendix 44

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