隨半導體製程技術快速發展，銅導線之寬度及間距亦不斷縮小，為防止銅原子擴散進入矽元件中造成元件特性退化，因此須在銅導線與介電層之間加入一擴散阻障層。擴散阻障層材料發展中，使用二元以上過渡金屬化合物、疊層結構或高熵合金作為擴散阻障層材料皆已有許多良好的研究成果；但隨銅製程進入20 nm以下，擴散阻障層厚度亦須降至3 nm以下，然均勻鍍覆超薄擴散阻障層具有難度，因此近年研究指出，透過自形成法製作擴散阻障層，再經由極短時間低溫熱處理後，少量元素自銅膜分離偏析至銅與介電材料界面處，即可自形成奈米等級超薄膜之優點，但迄今仍未有文獻探討固溶合金元素分離偏析行為。本研究利用磁控濺鍍法製備單元至多元合金與銅合金薄膜，分析合金與銅合金膜性質，再經低溫退火處理單元至多元銅合金薄膜，以釐清固溶合金元素分離偏析之行為。研究結果顯示，單元至多元銅合金薄膜經由熱處理，元素添加數目不同，固溶合金元素分離偏析之行為不同；由能量觀點來探討固溶合金元素數目不同對於合金元素分離偏析之行為影響。

With the rapid development of copper metallization technology, the line spacing of integrated circuits is drastically reduced. To prevent rapid Cu diffusion and silicide formation in interconnect structures, diffusion barriers are strongly demanded. In recent years, more stable and diffusion-resistant barriers have been intensively studied, including those of ternary components, of layered structures and of multi-principal components (high-entropy materials and their stacking structures). Due to the difficulty in uniform depositions of ultrathin barrier layers in nanoscale trenches, self-forming diffusion barriers (barrierless metallization) have further been developed in the past few years. The segregation of minor alloying elements in Cu films to Cu/dielectric interfaces under thermal annealing will self-form an ultrathin barrier layer. Thus in this study, Cu alloy films were deposited on Si substrates by magnetron sputtering, and alloyed solute elements would segregate during thermal annealing. Experimental results indicated that, in the six Cu alloy films, different solute segregation behaviors were observed under the competition of mixing enthalpy and mixing entropy. For the Cu(V) alloy film, the solute segregated to the Cu/Si interface, dominated by the large positive mixing enthalpy of V and Cu. For the Cu(V,Nb), the Cu(V,Nb,Mo) and the Cu(V,Nb,Mo,Ta) alloy films, the solutes formed intermetallic compounds due to the negative mixing enthalpies and the low-to-medium mixing entropies of the solute elements. For the Cu(V,Nb,Mo,Ta,Cr) alloy film, the solutes again segregated to the Cu/Si interface owing to the high mixing entropy of the solute elements.

誌謝 I
摘要 II
Abstract III
目錄 IV
圖目錄 VIII
表目錄 XII
壹、 前言 1
貳、 文獻回顧 3
2-1積體電路多層內連線及擴散阻障層 3
2-1-1電阻-電容延遲效應 (RC Delay) 3
2-1-2 金屬內連線材料 4
2-1-3擴散阻障層 (Diffusion Barrier Layer) 5
2-1-4傳統擴散阻障層材料 6
2-1-5二元以上過渡金屬化合物擴散阻障層 7
2-1-6過渡金屬化合物疊層結構擴散阻障層 8
2-2多元合金及氮化物擴散阻障層 11
2-2-1多元合金及氮化物薄膜特性 12
2-2-2多元合金及氮化物擴散阻障層 15
2-2-3多元合金及氮化物擴散阻障機制 18
2-2-3-1擴散行為之基本理論 18
2-2-3-2原子大小對晶格扭曲之影響 22
2-2-3-3元素鍵結能對整體鍵結能之影響 24
2-2-3-4原子大小對堆積密度之影響 26
2-3自形成擴散阻障層 28
2-3-1自形成擴散阻障層之發展 28
2-3-2自形成擴散阻障層之材料選擇條件 30
2-3-3自形成擴散阻障層之微結構 31
2-3-4自形成擴散阻障層之多元合金材料 33
2-4研究目的 36
參、 實驗步驟 37
3-1實驗規劃 37
3-2實驗步驟 38
3-2-1靶材製備 38
3-2-2基板準備 38
3-2-3 1A-6A多元厚膜沉積 42
3-2-4 1A-6A多元薄膜沉積 42
3-2-5 銅合金薄膜沉積 44
3-2-6氣氛熱處理 44
3-3分析儀器 45
3-3-1場發射電子微探儀 (FE-EPMA) 45
3-3-2 X 光繞射儀 (XRD) 45
3-3-3場發射掃描式電子顯微鏡 (FE-SEM) 46
3-3-4四點探針 (Four-Point Probe) 46
3-3-5高解析穿透式電子顯微鏡 (HR-TEM) 46
肆、 結果與討論 47
4-1 靶材晶體結構分析 47
4-2 多元合金膜之性質分析 49
4-2-1多元合金厚膜之性質分析 (鍍膜功率：50W) 49
4-2-1-1多元合金厚膜之成分分析 49
4-2-1-2多元合金厚膜之晶體結構 51
4-2-1-3多元合金厚膜之表面形貌 53
4-2-2多元合金薄膜之性質分析 (鍍膜功率：15W) 55
4-2-2-1多元合金薄膜之成分分析 55
4-2-2-2多元合金薄膜之晶體結構 57
4-2-2-3多元合金薄膜之表面形貌 59
4-2-3多元合金膜之綜合比較 61
4-2-3-1多元合金薄膜之電阻率 61
4-3銅合金薄膜分析 63
4-3-1成分分析與表面形貌 63
4-3-2晶體結構 66
4-3-3電阻率 68
4-4銅合金薄膜 (熱處理後) 之性質分析 70
4-4-1晶體結構 70
4-4-2表面形貌 72
4-4-3電阻率 74
4-4-4微結構 76
伍、 結論 85
陸、 參考文獻 87
柒、 附錄 94

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