氧化層微縮面臨:界面層造成等效氧化層厚度增加、可靠度及氧空缺導致臨界電壓下降等問題。本論文中分成三部份研究:利用界面層後高溫氮環境退火破壞矽氧鍵結脫附界面層、調變原子層沉積高介電層前驅物沉積時間鈍化氧空缺改善平帶電壓下降或增加氧空缺降低等效氧化層厚度以及利用金屬後退火溫度促使氧擴散還原界面層並探討退火溫度與氮源分壓之影響，探討對十六奈米鰭式電晶體電特性響。
第一部分，成長完界面層後進行不同秒數的大於1000°C高溫氮環境退火。針對高電壓操作的I/O規格鰭式電晶體，經退火後等效氧化層厚度下降成功脫附界面層。電晶體的汲極操作電流與轉導隨增加退火時間而提升，PFinFET經退火後改善漏電流、增加電洞遷移率且元件可靠度大幅提升推測界面層經退火後緻密化，但NFinFET因高溫損傷源極/汲極接面與介面導致漏電流、次臨界擺幅與可靠度退化。
第二部分，調變ALD high-K前驅物Metal precursor與Oxygen precursor的沉積時間改變高介電層內氧空缺分佈。針對高效能Core規格鰭式電晶體結果顯示，整體氧空缺較多的試片有最低的等效氧化層厚度但次臨界擺幅、遷移率與可靠度退化。表面氧空缺較少的試片改善臨界電壓標準差、漏電流與可靠度，但等效氧化層厚度增加令汲極操作電流與次臨界擺幅退化。表面氧空缺較多的試片改善平帶電壓下降、臨界電壓標準差、次臨界擺幅以及元件可靠度，並降低等效氧化層厚度提升汲極操作電流。
第三部分，調變金屬氮化物層後的退火溫度與環境分析對Core規格鰭式電晶體影響，增加退火溫度與降低環境氮源分壓導致等效氧化層厚度增加造成次臨界擺幅、汲極引致能障下降等退化。推測增加退火溫度界面層成長大於脫附能力，降低退火環境的氮源分壓將使更多氧從金屬氮化物擴散造成界面層成長。

There are several challenges about gate dielectric thickness scaling in MOSFET, such as increased equivalent oxide thickness(EOT) value due to the growth of interfacial layer(IL)、reliability, and oxygen vacancies induced threshold voltage(Vt) variation. This thesis consists of three parts to discuss the impacts on characteristics of gate stack process of 16 nm FinFET, which are interfacial layer desorption by high temperature annealing to reduce IL thickness and defects、reducing Vt variation by passivaMetal nitrideg oxygen vacancy at interface and reducing EOT by incorporating few oxygen vacancy into high-K with modulating oxygen content in atomic layer deposition(ALD), and scavenging IL by increasing oxygen diffusion with a post metal annealing(PMA) and effects of PMA temperature and nitrogen gas flow ratio on metal cap.
In the first parts, desorption of IL was carried out at high temperature for different annealing periods in N2 ambient. The desorption of IL in I/O FinFET can be obtained, which in confirmed by the reduced EOT. With increasing annealing time the on current and transconductance of devices increase. Reduced off current、enhanced mobility and reliability for PFinFET are achieved. The improvement may be attributed to the densification of IL after annealing. However, off current、subthreshold swing(S.S.), and mobility in NFinFET degrade after annealing. Which may be due to more diffusion in source draun junctions and defect generation at interface caused by a high temperature annealing.
In the second part, high-K deposition is formed with different Oxygen precursor and Metal precursor cycle time in ALD to tune the oxygen vacancy distribution. Results of Core FinFET show that the EOT decreases, but S.S.、mobility and reliability degrade for sample with oxygen vacancy rich at both interface and bulk. Sample with oxygen vacancy deficiency at interface shows improved Vt variance 、off current and reliability, but increased EOT induced degraded S.S. and on current. Sample oxygen vacancy rich at interface shows the reduced Vt roll off、reduced Vt variation and S.S. , and improved reliability. The on current also increases due to reduced EOT.
In the third part, PMA on metal nitride cap were performed at varies temperatures and gas ambients. EOT slightly increases with increasing anneal temperature and decreasing flow ratio of nitrogen gas, which induced S.S. and DIBL degradation. It may be attributed to interfacial layer regrowth with increasing the annealing temperature. IL regroeth caused by oxygen diffusion from metal nitride cap is more by decreasing nitrogen gas flow ratio in ambient.

目錄
摘要 I
Abstract II
致謝 IV
目錄 V
表目錄 VIII
圖目錄 IX
第一章 序論 1
1.1前言 1
1.2臨界尺度微縮議題 1
1.3 FinFET、high-K/Metal Gate、Raised strain S/D、Gate Last介紹 3
1.4 界面層脫附(Interfacial Layer Dissolve) 5
1.5 Interfacial Layer Scavenge 6
1.6 氧空缺(Oxygen Vacancy) 7
1.7論文架構 9
第二章 元件製程與量測 21
2.1 FinFET製造流程 21
2.1.1 FinFET標準製程 21
2.1.2 本論文研究製程 23
2.2電容與電晶體電性量測 23
2.2.1 電容電性量測 23
2.2.2 電晶體電性量測 24
2.2.3 可靠度量測 25
第三章 高溫氮環境退火脫附界面層對鰭式電晶體電特性研究 26
3.1研究動機 26
3.2製程與量測 27
3.2.1 製程條件 27
3.2.2 量測參數 28
3.3實驗結果與討論 28
3.3.1 1000°C 氮環境退火I/O電容電特性 28
3.3.2 1000°C 氮環境退火I/O電晶體電特性 29
3.3.3 1000°C 氮環境退火I/O電晶體可靠度量測 32
3.4結論 32
第四章 調變原子層沉積高介電層前驅物的沉積時間改變氧空缺分佈對鰭式電晶體電特性研究 48
4.1研究動機 49
4.2製程與量測 50
4.2.1 製程條件 50
4.2.2 量測參數 51
4.3實驗結果與討論 51
4.3.1 調變高介電氧空缺分佈 Core 電容電特性 51
4.3.2調變高介電氧空缺分佈Core 電晶體電特性 52
4.3.3調變高介電氧空缺分佈Core 電晶體可靠度量測 55
4.4結論 57
第五章 調變金屬後退火溫度與環境對鰭式電晶體電特性研究 75
5.1研究動機 75
5.2製程與量測 76
5.2.1 製程條件 76
5.2.2 量測參數 77
5.3實驗結果與討論 77
5.3.1 調變金屬後退火溫度與環境Core電容電特性 77
5.3.2 調變金屬後退火溫度與環境Core電晶體電特性 78
5.4結論 80
第六章 結論與未來展望 94
6.1結論 94
6.2未來展望 95
參考文獻 96

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