矽和鍺元素本身之間存在晶格常數的不匹配，可藉其自然晶格常數的差異來產生應力。若磊晶厚度在臨界厚度之下，可產生足夠應力以提升載子遷移率，故磊晶多層堆疊矽/鍺薄膜在SOI FinFET的通道上。由不同磊晶厚度之矽和鍺薄膜來產生不同的鍺含量在通道內之比例，形成具有矽鍺超晶格通道結構之鰭式電晶體元件，以達成更高的載子遷移率。本研究引進低溫微波作為離子佈植後之退火可達到好的活化摻雜退火，其製程溫度可以控制在400 ~500 oC左右。相較於傳統高溫快速熱退火，可抑制源極與汲極在摻雜活化後雜質擴散嚴重而造成短通道效應，也能抑制高介電係數介電層因高溫使等效氧化層厚度的增加。
第一部分，首先使用磊晶多層堆疊矽/鍺薄膜在SOI基板上，成功完成具有多層矽/鍺超晶格的鰭式電晶體元件。實驗結果發現，經過磊晶超晶格通道(2 Periods Si/Ge)之後的FinFET相較單晶矽的通道結構有更佳的電特性，電性上如較高的汲極電流、轉導值、Ion/Ioff ratio以及載子遷移率方面等，與較小的次臨界擺幅。推測原因是具有應力的鍺可提供較高載子遷移率，及有一層Si cap在通道上會使得鍺較不易擴散至介面。此外，發現以矽/鍺超晶格通道(2 Periods Si/Ge=25Å/25Å)在Ion/Ioff ratio、汲極電流、Gm、mobility的效果最好，整體皆明顯較優於其餘通道之元件，在矽鍺通道上成長一矽覆蓋層能提升應力、減少鍺向上擴散的現象。
第二部分，延續前一章節製作出矽/鍺超晶格通道(2 Periods Si/Ge=25Å/25Å)的電晶體元件。為了提升介面的電特性，使用低溫微波退火、高溫快速熱退火之不同活化摻雜方式，除了能達到活化效果外，期望低溫微波退火在閘極漏電流密度和介面特性獲得更進一步改善。實驗結果發現，使用低溫微波退火之元件的Tinv可達到1.6nm及閘極漏電流減少。再者，元件之關閉電流減低，是因為抑制了源極與汲極在摻雜活化後導致雜質擴散及漏電流。然而，元件之驅動電流在低溫微波退火相較於高溫快速熱退火會稍微較低。

A lattice mismatch exists between silicon and germanium material ,which induces a strain in Si/Ge channel FinFET. If a Ge epitaxy layer is under its critical thickness, a strain would be generated to promote carrier mobility. Epitaxy Si/Ge super-lattice is applied for SOI FinFET device in this thesis. Effects of Ge ratios in Si/Ge channel and are studied with different Si/Ge layer thicknesses as during epitaxy process.Higher carrier mobility in FinFET may be achieved by Si/Ge super lattice channel. A low-temperature microwave annealing is applied to achieve good activation after ion implantation, and its temperature can be around 400 ~500 oC . Compared to rapid thermal annealing , short channel effect induced by dopant diffusion can be suppressed by a microwave annealing for thermal activation . Also, the increases in equivalent oxide thickness of high-k dielectric layer after high temperature process may be minimized.
In the first part, Si/Ge multi-layers are epitaxially grown layer-by-layer on SOI substrate. FinFET with Si/Ge super lattice channel is successfully fabricated in this thesis. Experimental results show that electrical characteristics of device with Si/Ge super lattice are better as compared to those of control sample, such as higher drain current, transconductance , Ion/Ioff ratio and carrier mobility .The improvement can be attributed to the strained Si/Ge super lattice and suppressed Ge diffusion by Si cap. Moreover , electrical characteristics of device with Si/Ge super lattice channel formed by 2 Periods Si/Ge=25Å/25Å are the best among all samples, such as drain current, Ion/Ioff ratio, transconductance, mobility. Thus, Si cap on Si/Ge super lattice channel can achieve higher strain effect and lower Ge up-diffusion.
In the second part, FinFET with Si/Ge super lattice is used according to the results of the 1st part. In order to continuously promote electrical characteristics of FinFET, low-temperature microwave and rapid-thermal annealing treatments for dopant activation are investigated. Experimental results show that Tinv of 1.6nm and low gate leakage are achieved by a microwave annealing. Also, the off current of FinFET is reduced because the leakage current is suppressed by reducing dopants diffusion during activation process .However, the drain on current of device with a microwave annealing is smaller as compared to that with rapid thermal annealing.

摘要 I
Abstract III
致謝 V
目錄 VII
第一章 緒論 1
1.1前言 1
1.2使用High-k介電材料的原因 1
1.3高介電材料的選擇 2
1.4鰭式電晶體 3
1.5矽鍺虛擬基板-應變通道 4
1.6臨界厚度 4
1.7差排 5
1.8論文架構 6
圖1-1 介電層微縮下產生的問題(Re:K. Saraswat at Standford) 7
第二章 元件製程與量測 16
2.1 氧化鉿為介電層應用在Gate First SOI n-FinFET製作流程 16
2.1.1 晶片刻號 16
2.1.2 鰭式矽通道形成 16
2.1.3 磊晶矽鍺虛擬基板與閘極介電層沉積 17
2.1.4 金屬閘電極的形成 17
2.1.5 源極(Source)、汲極(Drain)、基極(Base)的形成 17
2.1.6 鈍化層沉積 18
2.1.7接出金屬導線、燒結 18
2.2 電性量測 18
2.2.1 金氧半電晶體的量測 18
第三章 磊晶矽鍺超晶格通道於矽在絕緣層上鰭式電晶體之電性研究 24
3.1研究動機 24
3.2製程與量測 25
3.2.1製程條件 25
3.2.2量測參數 29
3.3實驗結果與討論 29
3.3.1矽鍺超晶格通道在鰭式電晶體之電容電特性及電晶體元件分析 30
3.3.2矽鍺超晶格通道在鰭式電晶體之電特性分析 32
3.4結論 35
第四章 不同熱活化對矽鍺超晶格通道於矽在絕緣層上 之電性研究 50
4.1研究動機 51
4.2製程與量測 52
4.2.1製程條件 52
4.2.2量測參數 52
4.3實驗結果與討論 53
4.3.1使用不同活化摻雜方式在超晶格通道之電容電特性及電晶體元件之結構分析 53
4.3.2使用不同活化摻雜方式在超晶格通道之電特性分析 55
4.4結論 57
第五章 結論與展望 66
5.1結論 66
5.2未來展望 67
參考文獻 68

[1]M. Agostinelli,VLSI Tech, p. 232, 2010.
[2]Dieter K. Schroder, “Semiconductor Material and Device Characterization”, third edition, p. 342, 2006.
[3]J. H. Stathis, et al, IEEE IEDM, Vol. 71, p. 167, 1998
[4]Yuan Taur, et al., First published 1998, Reprinted, p.161, 1999.
[5]D.C. Houghton, J. Appl. Phys, Vol. 70, p. 2136, 1991
[6]M. Houssa, et al, Material Science and Enginerring R, p. 37, 2006
[7]H. S. Momose, et al., IEEE Trans. Electron Devices, vol. 43, p.1223, August 1996
[8]S, Saito, et al., IEEE IEDM, p. 797, 2003
[9]R. People , et al., App. Phys. Lett, Vol. 47, p. 322, 1985
[10]Niraj K. Jha, Electrical Engineering, Princeton University
[11]H.-S. Petitdidier, et al., Thin Solid Films,Vol. 476, p. 51, 2005
[12]S. Gupta, M.L. Lee,et al., Emergency Technologies, p. 61, 2005
[13]R. Zhang, North Carolina State University, Ph. D., p.1, 2006
[14]A. I. Kingon, et al, Nature 406, p. 1032, 2000
[15]Hiroaki Arimura, et al., Appl. Phys. Lett. 92,212902 ,2008
[16]Shin-ichi Takagi et al., IEEE Trans. Electron Devices, Vol. 41, NO.12, p. 2357, 1994
[17]University of Glasgow Semiconductor Device Group website
[18]C. Y. Kang, et al., IEEE International SOI Conference Proceedings, p. 135, 2006
[19]Hayashida et al., IEEE Trans. Electron Devices, Vol. 59, p. 647, March 2012
[20]Chang Yong Kang et al., IEEE Electron Device Letters, Vol. 29, p. 487, May 2008
[21]M. Yang et al., IEEE IEDM, p. 18.7.1, 2003
[22]C. Y. Kang, et al., IEEE IEDM, p. 1, 2006
[23]Georgios Vellianitis et al., IEEE Transactions on Electron Devices, Vol. 56, p.1548, No. 7, July 2009
[24]T.P.Ma et al., IEEE Trans. Electron Device, Vol. 45, p. 680, March 1998.
[25]R. Woltjer, et al., IEEE Trans. Electron Devices, Vol. 42, p. 109, 1995
[26]Tackhwi Lee, et al., IEEE Trans. Electron Devices, Vol. 58, NO. 2, p. 562, 2011
[27]Y. H. Xie. et al., Physical Review Letters, Vol. 73, No. 22, 1994
[28]Chia Ching Yeo, et al., IEEE Electron Device Letters, Vol. 26, No. 10, p. 761, 2005
[29]Erich Kasper et al., Thin Solid Films, Vol. 336, p. 319, 1998
[30]Goutam Kumar Dalapati, et al., IEEE Trans. Electron Devices, Vol. 53, No. 5, 2006
[31]Pei-Jer Tzeng, et al., IEEE Trans. Device and Materials Reliability, Vol. 5, No. 2, p. 168, 2005
[32]C. W. Liu, et al., Encyclopedia of Nanoscience and Nanotechnology, Vol. 9, p. 775, 2004
[33]Chee Wee Liu, et al., IEEE Circuit & Devices Magazine, 2005
[34]S. Maikap, et al., Solid-State Electronics, Vol. 44, p. 1029, 2000
[35]S. Maikap, et al., Semicond. Sci. Technol., Vol.15, p. 761, 2000
[36]Tung Ming Pan, et al., Appl. Phys. Lett. vol.78, p.1439, 2001
[37]C. D. Young, et al., IEEE Device and Materail Reliability, Vol.6, p. 123, 2006.
[38]Erich Kasper et al., Thin Solid Films, Vol. 336, p. 319, 1998
[39]Gareth Nicholson, et al., IEEE Electron Device Letters., Vol 28, p. 825, 2007
[40]Bahar, R.I et al., IEEE Trans. Electron Devices, Vol. 59, p. 807, March 2012
[41]Rui Zhang et al., IEEE IEDM, p. 28.3.4, 2011
[42]K. Rim, et al., IEEE VLSIT, p. 59, 2001
[43]C. R. Manoj et al.,IEEE Trans. Electron Devices, Vol. 55, p. 611, 2008
[44]B. Parvais et al., VLSI-TSA, p. 80, 2009
[45]S. M. Sze, , Second Ed. July, p.469
[46]Erich Kasper et al., Thin Solid Films, Vol. 336, p. 319, 1998E.
[47]D. A. Antoniadis, et al., IBM J. Res. & Dev, Vol. 50, p.363, 2006
[48]S.K. Ray, et al., Materials Science in Semiconductor Processing, Vol. 7, p. 203, 2004
[49]Tae-Sik Yoon, et al, Appl. Phys. Lett., Vol. 87, p.012104, 2005