純鍺基板是下一代MOSFETs的前瞻通道材料，因為鍺相較於矽而言，電子遷移率可提升兩倍、電洞遷移率可提升四倍。然而鍺半導體材料製程也存在許多困難，在高溫下鍺氧化層容易揮發及水解。鍺擴散到閘極介電層造成的閘極漏電流以及氧化鍺的界面是一個重要工程，解決這些問題是首要之務。此外，元件漏電流來源及鍺基板對溫度的敏感性是目前尚未清楚的。因此本論文藉由沉積不同high-K厚度以產生較高及較低的閘極漏電流，探討元件漏電流主要來源是閘極或PN接面漏電流。接著，透過最佳退火溫度處理抑制Ge MOSFETs元件漏電流主要來源。最後，希望在良好的元件特性及極低EOT下，透過改變燒結溫度來降低Ge MOSFETs漏電流及改善電特性。
　　第一部分，研究元件漏電流主要來源及high-K厚度對閘極和Ge MOSFETs元件漏電流影響。2.5 nm的HfON試片，其等效反轉氧化層厚度Tinv為6.5 Å，具有較大的閘極漏電流。5 nm的HfON試片，其等效反轉氧化層厚度Tinv為10 Å，具有較低的閘極漏電流，但卻有較高的元件漏電流。實驗結果顯示，漏電流主要來源是PN接面漏電流，由於元件漏電流並未因較厚的high-K厚度及較低閘極漏電流而降低。
　　第二部分中，利用ALD成長3 nm的HfON，可以得到極低的EOT。接著以離子佈值BF2形成源極及汲極後，進行退火處理降低其PN接面漏電流。實驗結果顯示，Ge P-MOSFETs透過RTA 450℃/ 30 sec退火處理可以得到PN接面在逆向偏壓為- 0.5 V下，漏電流為1.17 x 10^-6 A，元件漏電流為2.56 x 10^-9 A/um，元件的S.S.下降至136 mV/dec及On/Off ratio提高至10^4；界面層因Ge3+數量增加，閘極漏電流下降至2.58 x 10^-4 A/cm2，在RTA 450℃/ 30 sec下，載子遷移率最大值為375 cm2/V-sec。
　　第三部分中，延續前兩部分的實驗結果，希望鍺電晶體元件具有低PN接面漏電流、低閘極漏電流、低EOT、高載子遷移率的特性，進行Ge MOSFETs不同溫度的燒結。實驗結果顯示，燒結400℃/ 30 min會使其PN接面漏電流在逆向偏壓在- 0.5V下，提高至1.38 x 10^-6 A，元件漏電流提高為2.95 x 10^-9A/um，造成特性衰減。然而，Ge P-MOSFETs的Gm可以提高；另一方面，以300℃和350℃較低的燒結溫度，其PN接面漏電流較低，但Gm也會較低。

Germanium (Ge) is proposed as promising channel material in metal oxide semiconductor field effect transistor (MOSFETs) for next generation, because its electron and hole mobility are both higher than Si, which are about two and four times higher, respectively. However, there are many challenges to use Ge material. Ge oxide is easily volatilized and hydrolyzed at high temperature. Ge diffusion into gate dielectric would induce gate leakage, and Ge oxide quality for interfacial layer is a critical engineering. These issues should be resolved as the first priority. Besides, the root cause of leakage currents in device and temperature sensitivity of Ge substrate are not clear yet. Therefore, different high-K thicknesses are deposited to form devices with higher and lower gate leakage current in this thesis. Then, the root cause of leakage currents from gate or junction may be clarified. Next, the leakage currents in Ge MOSFETs could be suppressed by annealing treatments at optimal temperature. Ge MOSFETs with excellent characteristics and ultralow Equivalent Oxide Thickness (EOT) are hopefully obtained. Reduced leakage current and improved electrical characteristics in Ge MOSFETs would be achieved by sintering at suitable temperature.
In the first part, the root causes of leakage currents in Ge MOSFETs with various high-K thicknesses are studied. Sample with 2.5 nm thick HfON shows the electrical thickness in inversion (Tinv) of 6.5 Å and higher gate leakage. Sample with 5 nm thick HfON presents Tinv of 10 Å and lower gate leakage, which however has large off-state currents in Ge MOSFET. These results indicate that the junction leakage current is the root cause of leakage currents in Ge MOSFET, since the off-state current could not be decreased by a thicker high-K with lower gate leakage.
In the second part, a 3 nm thick HfON is grown by an Atomic Layer Deposition System (ALD), to obtain an ultralow EOT. Next, source and drain regions is formed by BF2 implantation, and a Rapid Thermal Annealing (RTA) is performed to reduce junction leakage. As a result, junction leakage current of 1.17 x 10^-6 A at reverse bias of - 0.5 V in Ge P-MOSFETs can be obtained by a RTA at 450℃ for 30s. Experimental results show that off-state current of 2.56 x 10^-9 A/um is obtained, sub-threshold swing (S.S.) is reduced to 136 mV/dec, and the On/Off ratio is increased to 10^4. The gate leakage current is decreased to 2.58 x 10-4 A/cm2, because there are more Ge3+ in the interfacial layer. Peak hole mobility of 375 cm2/V-sec is achieved by a RTA at 450℃.
In the third part, different sintering temperatures on Ge MOSFETs are studied with the optimal RTA condition in previous works. Device with low junction leakage current, low gate leakage current, low EOT, and high mobility may be obtained. Junction leakage current is increased to 1.38 x 10^-6 A at reverse bias of - 0.5 V in device with sintering at 400℃ for 30 min. The off-state current is obtained 2.95 x 10^-9 A/um, which might degrade device characteristics. However, transconductance (Gm) could be improved in Ge P-MOSFETs. On the other hand, a lower sintering temperature, for example 300℃, 350℃, would decrease junction leakage but Gm is decreased.

摘要 I
致謝 V
目錄 VI
表目錄 IX
圖目錄 X
第一章　序論 1
1.1 前言 1
1.2 使用鍺基板作為載子通道材料 1
1.3 高介電係數(high-K)介電材料導入的原因 2
1.4 高介電係數(high-K)材料的選擇 3
1.5 界面缺陷鈍化(Interface defect passivation) 4
1.6 界面層的形成方式 6
1.7 原子層沉積系統(Atomic Layer Deposition System) 7
1.8 論文架構 8
第二章　元件製程與量測 15
2.1 鉿薄膜緩衝層及HfON介電層的純鍺基板P-MOSFETs元件製程流程 15
2.1.1 實驗前晶片清洗 15
2.1.2 以H2O plasma成長之GeO2界面層與鉿薄膜緩衝層/閘極介電層沉積 16
2.1.3 金屬閘電極與接觸電極的形成 16
2.1.4 源極(Source)、汲極(Drain)、基極(Base)的形成 16
2.1.5 接出金屬導線、燒結 17
2.2 電性量測 18
2.2.1 金氧半電晶體的量測 18
2.3 物性分析 20
2.3.1 X光繞射儀 20
2.3.2 X射線光電子能譜儀 20
2.3.3 穿透式電子顯微鏡 21
第三章　鍺金氧半電晶體介電層厚度對閘極及元件漏電流影響 23
3.1 研究動機 23
3.2 製程與量測 24
3.2.1 製程條件 24
3.2.2 量測參數 26
3.3 實驗結果與討論 26
鍺金氧半電晶體介電層厚度對閘極及元件漏電流影響分析 26
3.4結論 29
第四章　以最佳退火溫度降低鍺金氧半電晶體漏電流研究 38
4.1 研究動機 39
4.2 製程與量測 39
4.2.1 製程條件 39
4.2.2 量測參數 41
4.3 實驗結果與討論 41
4.3.1 以最佳退火溫度降低鍺金氧半電晶體漏電流電特性分析 41
4.3.2 以最佳退火溫度降低鍺金氧半電晶體漏電流物理特性分析 45
4.4 結論 48
第五章　燒結溫度對鍺金氧半電晶體漏電流及電特性影響研究 71
5.1 研究動機 72
5.2 製程與量測 72
5.2.1 製程條件 72
5.2.2 量測參數 74
5.3 實驗結果與討論 74
燒結溫度對鍺金氧半電晶體漏電流及電特性影響分析 74
5.4 結論 78
第六章　結論與展望 90
6.1 結論 90
6.2 未來展望 91
參考文獻 92

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