現代半導體工藝技術隨著摩爾定律(Moore’s law)的預期發展，其中短通道性應一直都是一道難以突破的瓶頸。因此，元件從原本使用已久的二維結構轉變為閘極控制能力較佳的三維結構，即廣為人知的鰭式場效電晶體(FinFET)。
在本研究中主要針對摻雜濃度(Doping concentration)固定的情況下，調整鰭式場效電晶體結構參數，以配合元件設計調整使用。其中包含隔離層長度(Spacer, LSP)、鰭式通道頂部寬度(Top Fin-Width, FWT)、鰭式通道底部寬度(Bottom Fin-Width, FWB)以及鰭式通道高度(Fin-Height, FH)。
模擬結果顯示，隔離層的長短會大大的影響整體元件的電特性，並且隨著閘極長度(LG)的不同而有不一樣的影響，因此必須隨著需求而調整隔離層長度，本研究為簡化問題，將針對隔離層固定的情況下，探討各種結構參數對電特性之影響。
一般認為，提高鰭式通道高度可以有效增加飽和電流(ISAT)，提高一奈米的高度約可得到兩個百分點左右的電流增益，提高其值並不太影響臨界電壓值(VTH)是其優勢之一，但其值越高代表著深寬比(Aspect ratio)越大，使製程難度提升許多。
接下來是鰭式通道底部寬度的部分，可發現增寬其值並沒有辦法有效提高電流，增寬一奈米的寬度所得到的電流增益僅為一個百分點；雖然越寬的鰭式通道底部寬度可以讓往後源極、汲極的磊晶容易許多，但卻也提高整體元件面積，和現今半導體工藝所需背道而馳。
調整鰭式通道頂部寬度為最有效之提高電流之選擇，多一奈米的寬度所得到的電流增益為四個百分點，是三個選項中的最高值；再者調整鰭式通道頂部寬度並不太影響臨界電壓值，且其越寬也有利往後源極、汲極的磊晶。
總而言之，本研究提出了幾種提高飽和電流的選擇，並分析其影響其他電性的可能。最後得出，鰭式場效電晶體可以有效延續摩爾定律到五奈米節點之結論。

In modern semiconductor industry, it keeps following Moore’s law. Short channel effects (SCE) has always been a serious issue to familiar with. As a result of this, CMOS device turned form traditional two-dimensional (2D) structure into a three-dimensional (3D) structure, which is well known as FinFETs.
This study, we describe some strategies to design CMOS devices by tuning FinFET structure to gain better electrical properties with same doping concentration. The structure parameters including spacer length (LSP), Top Fin-Width (FWT), Bottom Fin-Width(FWB) and Fin-Height (FH).
The simulation result shows that LSP will largely affect device electrical properties, and it will be different as gate length (LG) changing. The LSP should be design to fit the requirement. To simplify the mission, this research focuses on a fixed LSP condition and varies other structure parameters.
It is well known that, increasing FH can effectively gain saturation current(ISAT). A 1 nm increment of FH approximately can gain additional 2% current. One of its advantages is that it would not affect threshold voltage (VTH) a lot. But a higher FH means that a larger aspect ratio, thus a harder manufacturing process.
Increasing FWB to gain current may not be a good choice due to its inefficient. It can only gain additional 1% current. Even a wider FWB lets a larger cross section for epitaxy source and drain, but it also increases device area, which contradicts the requirement of modern semiconductor industry.
Tuning FWT may be the best choice to have a current gain. Additional 1 nm FWT can gain extra 4% current, which is the highest in these three options. Moreover, it would not influence VTH a lot, and it is good for source drain epitaxy.
In conclusion, this study suggests some options to gain current. We also analyze how these strategies influence electrical properties. Finally, we conclude that FinFET can continue Moore’s till 5 nm technology node.

中 文 摘 要 i
Abstract iii
Acknowledge v
Chapter 1 1
Introduction 1
1-1 The challenge of the Moore’s Law 1
1-2 Challenges of traditional MOSFET 4
1-3 Motivation 8
1-4Thesis Organization 14
Chapter 2 15
Multi-gate FET and Nano-device Mechanism 15
2-1 Multigate FETMechanism 15
2-2 Quantum Mechanism 19
2-3 Device Leakage 26
Chapter 3 31
Device Structure and Simulation 31
3-1 Device Structure 31
3-2 Device Parameters Setting and Strategy 33
Chapter 4 36
Results and Discussion 36
4-1 Trigate FinFETs with Different Spacer Length 37
4-2Trigate FinFETs with Different Fin-Height 40
4-3Trigate FinFETs with Different Fin-Width 41
4-4Trigate FinFETs with Different Top-Fin-Width and Different Fin-Height 45
4-5 Physical Properties Analysis of FWT and FH 52
4-6 Electric Properties of each technology nodes FinFETs 61
Chapter 5 64
Conclusion 64
Reference 66

1-1. sensics, OSVR - Open Source Virtual Reality, from
(http://sensics.com/portfolio-posts/osvr-open-source-virtual-reality/)
1-2. Intermolecular, Logic device roadmap, from(http://intermolecular.com/)
1-3. Disrupted electronics... the internet of things may create Moore’s Law on steroids, from (http://idisrupted.com/disrupted-electronics-internet-things-may-create-moores-law-steroids/)
1-4. C.-H. Jan, U. Bhattacharya, R. Brain, S.-J. Choi, G. Curello, G. Gupta, et al., "A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications," in Electron Devices Meeting (IEDM), 2012 IEEE International, 2012, pp. 3.1. 1-3.1. 4.
1-5. SOI industry consortium, Bulk VS SOI FinFET, from
(http://www.soiconsortium.org/videos/bulk-vs-soi-finfet/)
1-6. A. R. Brown, N. Daval, K. K. Bourdelle, B.-Y. Nguyen, and A. Asenov, "Comparative simulation analysis of process-induced variability in nanoscale SOI and bulk trigate FinFETs," IEEE Transactions on Electron Devices, vol. 60, pp. 3611-3617, 2013.
1-7. C.-W. Sohn, C. Y. Kang, M.-D. Ko, R.-H. Baek, C.-H. Park, S.-H. Kim, et al., "Effect of fin height of tapered FinFETs on the sub-22-nm System on Chip (SoC) application using TCAD simulation," in VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on, 2013, pp. 1-2.
1-8. B. D. Gaynor and S. Hassoun, "Fin shape impact on FinFET leakage with application to multithreshold and ultralow-leakage FinFET design," IEEE Transactions on Electron Devices, vol. 61, pp. 2738-2744, 2014.

Chapter 2

2-1. J.-P. Colinge, FinFETs and other multi-gate transistors vol. 73: Springer, 2008.
2-2. V. P. Trivedi and J. G. Fossum, "Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs," IEEE Electron Device Letters, vol. 26, pp. 579-582, 2005.
2-3. L. Chang, S. Tang, T. King, J. Bokor, and C. Hu, "Gate length scaling and threshold voltage control of double-gate MOSFETs Electron Devices Meeting, IEDM Technical Digest," International Dec, p. 719, 2000.
2-4. S.-i. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, S. Nakaharai, T. Numata, et al., "Sub-band structure engineering for advanced CMOS channels," Solid-State Electronics, vol. 49, pp. 684-694, 2005.
2-5. V. De and S. Borkar, "Technology and design challenges for low power and high performance," in Proceedings of the 1999 international symposium on Low power electronics and design, 1999, pp. 163-168.
2-6. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits," Proceedings of the IEEE, vol. 91, pp. 305-327, 2003.
2-7. A. Keshavarzi, K. Roy, and C. F. Hawkins, "Intrinsic leakage in low power deep submicron CMOS ICs," in Test Conference, 1997. Proceedings, International, 1997, pp. 146-155.
2-8. X. Yuan, J.-E. Park, J. Wang, E. Zhao, D. C. Ahlgren, T. Hook, et al., "Gate-induced-drain-leakage current in 45-nm CMOS technology," IEEE Transactions on Device and Materials Reliability, vol. 8, pp. 501-508, 2008.

Chapter 3
3-1. User’s Manual for Synopsys Sentaurus Device.
3-2. TCAD Sentaurus Device, Ver. E-2010.12, Synopsys, Inc., Mountain View, CA, USA, Mar. 2011.
3-3. Mark Lundstrom ,"Emerging CMOS Technology at 5 nm and Beyond: Device Options and Trade-offs," in Electron Devices Meeting (IEDM) short course, 2015IEEE International, 2015.
Chapter 4
4-1. Y. Li and C.-H. Hwang, "Effect of fin angle on electrical characteristics of nanoscale round-top-gate bulk FinFETs," IEEE Transactions on Electron Devices, vol. 54, pp. 3426-3429, 2007.
Chapter 5
5-1 N. Horiguchi, A. Milenin, Z. Tao, H. Hubert, E. Altamirano-Sanchez, A. Veloso, et al., "Patterning challenges in advanced device architectures: FinFET to nanowire," in SPIE Advanced Lithography, 2016, pp. 978209-978209-10.
5-2 M. Salmani-Jelodar, S. R. Mehrotra, H. Ilatikhameneh, and G. Klimeck, "Design guidelines for sub-12 nm nanowire MOSFETs," IEEE Transactions on Nanotechnology, vol. 14, pp. 210-213, 2015.