基於鍺材料有更高的載子遷移率，可用來提升驅動電流。所以利用NDL 實驗室內之超高真空化學氣相磊晶(UHVCVD)獲得鍺虛擬基板。但鍺表面易形成不穩定的氧化物且磊晶薄膜有較高的缺陷密度，故之後使用即場氣體電漿處理在界面層來改善電特性。
第一部分，使用磊晶成長Ge buried channel在 SOI FinFET 電晶體之上。在ALD 機台in-situ使用不同氣體(CF4/NH3/H2)電漿對界面層處理。CF4電漿處理能促使high-k由單斜晶重新結晶為正方晶，獲得較大的k值。使用NH3電漿處理後，能氮化界面層，降低漏電流與EOT。經過H2電漿處理，會減少表面懸鍵與修補界面缺陷。由實驗結果得知以CF4電漿處理在導通電流(on current)優於其他電漿處理的元件。但經過CF4電漿 處理會使得漏電流變大，此為後續實驗所著重重點。
第二部分，一樣先使用UHVCVD以平面性的磊晶方式磊Ge buried channel，再 蝕刻出鰭式結構。延續第一節為了改善CF4的漏電問題且維持高的導通電流，我們先通CF4電漿來獲得高導通電流再使用H2或NH3電漿來修補界面缺陷以減少Dit。實驗結果可以發現，經過CF4+H2之後的 FinFET 較CF4+NH3或純CF4試片有更好的電特性， 如較高的汲極電流、轉導值以及較低的S.S.。

The on current of MOSFETs can be improved by Ge channel, because its carrier mobility is higher than Si. Thus, an epitaxy Ge buried channel is applied in this thesis. The epitaxy layer is successfully grown by the ultrahigh vacuum chemical molecular epitaxy (UHVCVD) in National Nano Device Laboratories (NDL). However, unstable Ge sub-oxide is easily formed on Ge surface and the epitaxy Ge film has many defects. So in-situ plasma treatments are applied on interfacial layer to improve electrical properties of Ge MOSFETs.
In the first part, Ge buries channel is epitaxially grown layer-by-layer on Si SOI to form FinFET. And then, in-situ gas plasma (NH3/CF4/H2) treatments are applied on interfacial layer (IL) in Atomic Layer Deposition (ALD). CF4 plasma may transform some of the high-k from monoclinic to tetragonal, which can improve the k-value. After NH3 plasma treatment, the nitridation of IL can suppress leakage current and achieve smaller EOT. And H2 plasma can psssivate the Ge surface and reduce the dangling bonds at IL/Ge; Results show that electrical characteristics such as on current, Ion/Ioff ratio in CF4 sample are improved, but its leakage current is also increased. Thus, the following task would try to suppress leakage current.
In the second part, SOI FinFET with Ge buried channel is also studied, and the serious leakage current caused by CF4 plasma treatment will be resolved. After CF4 plasma treatment, further in-situ H2 or NH3 plasma treatment is applied to passivate the IL damages and reduce interface trap density (Dit). Results show that the CF4+H2 treatment is helpful to obtain better electrical characteristics compared to CF4+NH3 and CF4 sample, in terms of such as drain on current and subthreshold swing.

摘要 I
Abstract II
致謝 III
目錄 IV
表目錄 VII
圖目錄 VIII
第一章 緒論 1
1.1前言 1
1.2使用High-k介電材料的原因 1
1.3高介電材料的選擇 2
1.4 絕緣層覆矽基板 3
1.5鰭式電晶體 3
1.6矽鍺虛擬基板-應變通道 4
1.7臨界厚度 4
1.8差排 5
1.9論文架構 6
第二章 元件製程與量測 17
2.1 氧化鉿為介電層應用在Gate First SOI n-FinFET製作流程 17
2.1.1 晶片刻號 17
2.1.2 磊晶鍺虛擬基板與鰭式鍺通道形成 17
2.1.3 in-situ氣體電漿處理與閘極介電層沉積 18
2.1.4 金屬閘電極的形成 18
2.1.5 源極(Source)、汲極(Drain)、基極(Base)的形成 18
2.1.6 鈍化層沉積 19
2.1.7 接出金屬導線、燒結 19
2.2 電性量測 19
2.2.1 金氧半電晶體的量測 19
2.3 物性分析 21
2.3.1 X光繞射儀 21
2.3.2 X射線光電子能譜儀 21
第三章 以鍺作為通道且使用in-situ電漿處理製作於絕緣層上矽鰭式電晶體之電性研究 27
3.1研究動機 28
3.2製程與量測 29
3.2.1製程條件 29
3.2.2量測參數 32
3.3實驗結果與討論 32
3.3.1鍺作為通道於鰭式電晶體之電晶體元件之材料分析 33
3.3.2鍺作為通道於鰭式電晶體之相同閘極電容之電特性分析 35
3.3.3 Ge+Si cap作為通道於鰭式電晶體之電特性分析 36
3.3.4 Ge+Si cap作為通道於鰭式電晶體之可靠度分析 38
3.4結論 39
第四章 不同組合之氣體電漿處理對磊晶鍺通道於絕緣層覆矽鰭式電晶體之電性研究 54
4.1研究動機 55
4.2製程與量測 55
4.2.1製程條件 55
4.2.2量測參數 56
4.3實驗結果與討論 56
4.3.1鍺作為通道於鰭式電晶體之相同閘極電容之電特性分析及電晶體元件之結構分析 56
4.3.2使用不同氣體電漿處理方式在以Ge+Si cap為通道之SOI n-FinFET之電特性分析 58
4.3.3使用不同氣體電漿處理方式在以Ge+Si cap為通道之SOI n-FinFET之可靠度分析 61
4.4結論 62
第五章 結論與展望 71
5.1結論 71
5.2未來展望 72
參考文獻 73

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