現代電子產品功能不斷擴張，強調多功能、體積小及重量輕等訴求，造成產品中的電晶體必須不斷微縮以符合市場需求，而在微縮過程中短通道效應、製程技術以及物理極限將是一般傳統電晶體將會面臨的挑戰，無接面電晶體是一種未來可解決這些困難的新穎元件，無接面電晶體的特點就是其源極、汲極以及通道摻雜型態以及濃度皆相同。因此此電晶體除了可以減少製程步驟、降低熱預算之外，還能降低短通道效應。
因此在本篇論文中，提出了混合溝槽式多晶矽無接面場效電晶體搭配環繞式閘極作探討，使用混合式結構是藉由基板與通道在垂直方向上產生的接面造成等效通道厚度減少，另外沉積較厚的非晶矽，接著有效退火利用後使用乾式蝕刻的非等向性方式對多晶矽通道進行薄化，形成溝槽式的超薄主動層。相較於傳統直接沉積超薄多晶矽主動層的方式可以得到較大的晶粒與較少的晶界。在形成超薄溝槽式主動層時，抬升式源汲極結構也同時完成。再搭配上環繞式閘極增加閘極控制能力，提升元件開關能力以及降低漏電流。
本篇論文開發出混合式無接面電晶體結構搭配溝槽式通道有著環繞式閘極和奈米線(Nanowires)結構之多晶矽無接面薄膜電晶體。此元件展現了極佳的電特性，像是陡峭之次臨界擺幅(Subthreshold swing, SS)136mV/dec.、較高的開關電流比(Ion/Ioff current ratio>106)、較低的汲極引致能障下降值 (Drain-induced barrier lowering, DIBL)為60mV/V，此外本結構對I-V特性對溫度有加以探討，接著再使用T-cad模擬軟體比較有無溝槽式結構的電性，結果為溝槽式結構有較好的開關電流比。
提出此混合溝槽式多晶矽無接面場效電晶體搭配環繞式閘極之研究有良好的電特性且製程非常簡單容易，因此非常有機會在應用在未來三維堆疊結構與低消耗功率元件上做搭配。

Modern electronic devices become more and more useful, emphasizing on multifunctional, small size, light weight, etc. as the feature size of logic device has been scaled continuously, conventional inversion-mode Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) face a lot of challenges such as random dopant fluctuation, physical limitation and short channel effect (SCE). Junctionless FET is the one of the solution in the future devices. JL-FET is a novel device, which has heavily doping channel with the same type to that of source and drain. Therefore, JL-FE has a slight (SCEs) and less thermal budget in process of fabrication.
In this thesis, hybrid p-channel poly-Si Junctionless field-effect transistors with trench and gate-all-around structure are proposed and fabricated. The hybrid structure makes the thinner effective channel thickness owing to the depletion layer by the channel and substrate. Besides, the annealing after depositing the thick amorphous silicon and use the anisotropic reactive ion etch to form the polycrystalline silicon (poly-Si) UTB. The RIE thinning process could get larger grain size and less grain boundary than directly depositing the thin-film. After RIE thinning process, the nanowires look like the trench structure and the raise S/D structure is completed at the same time.. In addition, gate-all-around (GAA) structure combine with UTB could improve gate control ability, which improve sub-threshold swing (SS) and reduce OFF-state leakage current.
The hybrid poly silicon channel junctionless field-effect-transistors with trench structure have ten nanowires with gate-all-around structure. The performance of the device is excellent with the steep sub-threshold swing (SS) (136mV/dec.), the high current ratio (Ion/Ioff current ratio>106), and lower DIBL (60mV/V); then, discuss the electrical characteristics in variable temperature with every 25oC as a step from the 50oC to 200oC, finally, we use Sentaurus TCAD to compare trench structure with without trench structure, the result shows use trench structure can get higher ION/IOFF ratio than without trench structure.
The proposed hybrid JL-FETs with trench structure not only the easy fabrication but also has the good characteristics for advanced low power consumption applications and three-dimensional (3-D) stacked ICs applications.

中文摘要 - I
Abstract - III
Acknowledge - V
Contents - VI
Figure Captions -VIII
Chapter 1 - 1
Introduction - 1
1-1 More than Moore - 1
1-2 Introduction of Junctionless Device - 4
1-3 Motivation - 12
1-4 Thesis Organization - 17
Chapter 2 - 19
Junctionless Mechanism - 19
2-1 Basic Principle of Junctionless Transistor - 19
2-2 Short Channel Effects in Junctionless transistor - 26
2-3 The Temperature Performance of Junctionless - 28
High temperature - 28
Chapter 3 -30
Device Fabrication and Structure - 30
3-1 Device Fabrication Process - 30
3-2-1 SEM and AFM image of device structure - 33
3-2-2 TEM image of device structure - 37
Chapter 4 - 39
Characteristics Analysis - 39
4-1 Characteristics Analysis for hybrid GAA and Planar device - 39
4-2 Device Temperature Performance - 48
4-3 Device Simulation - 50
Chapter 5 - 53
Conclusion - 53
Reference - 55

Chapter 1
[1-1] G. E. Moore, “Cramming more components onto integrated circuits,” Proceedings of the IEEE, vol. 86, pp. 82-85, 1965
[1-2] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.
[1-3] Horng-Chih Lin, Senior Member, IEEE, Cheng-I Lin, Zer-Ming Lin, Bo-Shiuan Shie, and Tiao-Yuan Huang, “Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 3, MARCH 2013
[1-4] Shinji Migita, Yukinori Morita, Meishoku Masahara, and Hiroyuki Ota, “Electrical Performances of Junctionless-FETs at the Scaling Limit (LCH = 3 nm),” Electron Devices Meeting (IEDM), 2012 IEEE International, 2012,
[1-5] H. T. Lue, T. H. Hsu, Y. H. Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S. Y. Wang, J. Y. Hsieh, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, and C. Y. Lu, “A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device,” in VLSI Symp. Tech. Dig., pp. 131–132, 2010.
[1-6] Jean-Pierre Colinge, “Multiple-gate SOI MOSFETs,” Solid-State Electronics 48, 2004, 897–905.
[1-7] Bio KIM, Seung-Hyun LIM, Dong Woo KIM, Toshiro NAKANISHI, Sangryol YANG, Jae-Young AHN, Han Mei CHOI, Kihyun HWANG, Yongsun KO, Chang-Jin KANG, “Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash”, Reliability Physics Symposium (IRPS), IEEE International,., pp. 126-129, 2011.
[1-8] Mu-Shih Yeh, Yung-Chun Wu, Min-Hsin Wu, Yi-Ruei Jhan, Ming-Hsien Chung, and Min-Feng Hung, “High Performance Ultra-Thin Body (2.4nm) Poly-Si Junctionless Thin Film Transistors with a Trench Structure”, Electron Devices Meeting (IEDM), 2014, pp. 618-621.
[1-9] Y.-C. Cheng, H.-B. Chen, J.-J. Su; C.-S. Shao ; Thirunavukkarasu, V., C.-Y. Chang, and Y.-C. Wu, “Characteristics of a novel poly-Si P-channel junctionless thin-film transistor with hybrid P/N-Substrate,” IEEE Electron Device Lett., vol. 36, no. 2, pp.159–161, Feb. 2015.

Chapter 2
[2-1] J.P. Colinge, Semiconductor-On-Insulator Materials for NanoElectronics Applications, chapter 10, pp.187, 2011.
[2-2] J. P. Colinge, C. Lee, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, A. Kranti, and R. Yu, Junctionless Transistors: Physics and Properties, Semiconductor-On-Insulator Materials for Nanoelectronics Applications. New York, NY, USA: Springer-Verlag, 2011, pp. 187–200.
[2-3] C.-W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, and J. P. Colinge, “Performance estimation of junctionless multigate transistors,” Solid-State Electron., vol. 54, no. 2, pp. 97–103, Feb. 2010.
[2-4] P. Razavi, G. Fagas, I. Ferain, R. Yu, S. Das, and J. P. Colinge, “Influence of channel material properties on performance of nanowire transistors,” Journal of Applied Physics, vol. 111, no. 12, pp. 124509-1–124509-8, 2012.
[2-5] C.-W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, and J. P. Colinge, “High temperature performance of silicon junctionless MOSFETs,” IEEE Trans. Electron Devices, vol. 57, no. 3, pp. 620–625, Mar. 2010.

Chapter 4
[4-1] C.-W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, and J. P. Colinge, “High temperature performance of silicon junctionless MOSFETs,” IEEE Trans. Electron Devices, vol. 57, no. 3, pp. 620–625, Mar. 2010.
[4-2] TCAD Sentaurus Device, Ver.G-2012.06, Synopsys 2012.

Chapter 5
[5-1] Bio KIM, Seung-Hyun LIM, Dong Woo KIM, Toshiro NAKANISHI, Sangryol YANG, Jae-Young AHN, Han Mei CHOI, Kihyun HWANG, Yongsun KO, Chang-Jin KANG, “Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash”, Reliability Physics Symposium (IRPS), IEEE International,., pp. 126-129, 2011.
[5-2] Hung-Bin Chen1, Yung-Chun Wu, Chun-Yen Chang, Ming-Hung Han, Nan-Heng Lu, and Ya-Chi Cheng, “Performance of GAA poly-Si Nanosheet (2nm) channel of Junctionless Transistors with ideal Subthreshold Slope,” in VLSI Symp. Tech. Dig., pp. 232-233, 2013.
[5-3] Shinji Migita, Yukinori Morita, Meishoku Masahara, and Hiroyuki Ota, “Electrical Performances of Junctionless-FETs at the Scaling Limit (LCH = 3 nm),” Electron Devices Meeting (IEDM), 2012 IEEE International, 2012.