當電晶體微縮到低於20 nm 以下，傳統的MOSFET會出現次臨界漏電流、閘極漏電流等的問題。這些問題可以藉由鰭式電晶體的結構克服。鰭式電晶體有較好的電特性，因其通道外型高而薄。本論文主要應用氫電漿及高溫處理的效應。氫電漿作用在矽表面，有輕微蝕刻的效果，有助於使通道側壁垂直，名為trimming，可提高電晶體電特性。再者，矽經過高溫處理，通道上層趨圓滑，能降低尖端放電，使電特性提升。
第一部分，主要為利用實驗室之前成功建立的一套SOI n-FinFET標準製程。Trimming在矽鰭式電晶體的矽通道上，並改變不同氫氣電漿處理時間，來得到較垂直的結構做探討。整體S.S維持在65~75 mV/dec之間。300sec的氫氣trimming處理元件的電特性較標準元件提升。另一方面，使用1200sec的氫氣trimming處理元件的電性反而會下降。例如，300sec的氫氣trimming處理元件閘極漏電流密度約2.94x10-7 A/cm2、轉導值約32 µA/V及載子最大遷移率約413 cm2/V-sec。標準式片及300sec的氫氣trimming處理元件表現良好，臨界電壓飄移特性的表現都維持在25mV左右。1200sec的氫氣trimming處理元件臨界電壓飄移量則會稍大。
第二部分，為利用不同高溫處理之方式試圖使上層通道越趨圓滑。實驗結果發現，隨著通道處理溫度的增加，電性得以改善。整體S.S維持在60~70 mV/dec之間，可見元件整體閘極控制能力表現不錯。使用高溫處理900℃之元件之元件的可達最低的次臨界擺幅最低約64.3 mV/dec、最低閘極漏電流密度約3.13x10-8 A/cm2、最大汲極電流約8.9x10-5 μA/μm、最大轉導值約114.7μA/V 及載子最大遷移率約488 cm2/V-s。再者，在可靠度方面，經過加壓後的高溫處理900℃之元件臨界電壓飄移量最小。其餘元件在臨界電壓飄移較大。

When transistors’ feature sizes scale down lower than 20 nm, conventional MOSFET confront some issues such as the effects of subthreshold leakage, gate leakage, and so on. These issues can be resolved by FinFET structure. The electrical characteristics of FinFET can be bettter if its channel shape is high and thin. Effects of hydrogen plasma and high temperature treatment are studied in this thesis. When hydrogen plasma treatment is aplied on silicon surface, a slight etching could make channel more vertical, namely trimming, and enhances electrical characteristics of device. Moreover, when a high temperature treatment is applied on silicon, channel surface would become smoother, which reduces corona discharge and improves electrical characteristics.
In the first part, SOI n-FinFET is successfully fabricated based on our previous work. A trimming process on silicon channel of FinFET is studied with different time of hydrogen plasma treatements to get a more vertical structure. Results show that subthreshold swing values of all devices are about 65 to 75 mV/dec. Electrical characteristics of device with 300 s trimming are better than those of control one. On the contrary, device with 1200 s trimming show worse performance. Device with 300 s trimming has better performance, demonstarting such as, gate leakage of about 2.94x10-7 A/cm2, transconductance of 32 μA/V and peak carrier mobility of 413 cm2/V-sec. Reliability characteristics of control sample and devices with 300 s trmming are good, showing threshold voltage shift of about 25 mV. Device with 1200 s trimming suffers a much higher threshold voltage shift.
In the second part, in order to continuously promote device characteristics, a high temperature treatment on FinFET is applied to make channel shape smoother. Experimental results show that electrical characteristics are improved with increasing treatment temperature. All samples show subthreshold swing values of about 60 to 70 mV/dec, indicating good gate control capability. Devices with 900℃ treatment have lowest subthreshold swing of 64.3 mV/dec, lowest gate leakage of 3.13x10-8 A/cm2, highest on current of 8.9x10-5 μA/μm, highest transconductance of 114.7μA/V and highest carrier mobility of 488 cm2/V-sec. Moreover, for reliability characteristics, device with 900℃ treatment performs a smaller threshold voltage shift after stressing. The other devices perform higher threshold voltage shifts.

摘要 I
Abstract II
目錄 IV
表目錄 IX
圖目錄 X
第一章 緒論 1
1.1前言 1
1.2使用High-k介電材料的原因 1
1.3高介電材料的選擇 2
1.4鰭式電晶體 3
1.5氫氣電漿處理的影響 3
1.6尖端放電效應的影響 4
1.7論文架構 4
第二章 元件製程與量測 14
2.1 氧化鉿為介電層應用在Gate First SOI n-FinFET製作流程 14
2.1.1 晶片刻號 14
2.1.2鰭式矽通道形成 14
2.1.3氫氣電漿Trimming矽通道輪廓處理 15
2.1.4閘極介電層沉積 15
2.1.5金屬閘電極的形成 15
2.1.6源極(Source)、汲極(Drain)、基極(Base)的形成 16
2.1.7 鈍化層沉積 16
2.1.8接出金屬導線、燒結 16
2.2 電性量測 17
2.2.1 金氧半電晶體的量測 17
第三章 不同氫氣電漿處理時間對矽鰭式場效電晶體之電性影響研究 25
3.1研究動機 25
3.2製程與量測 27
3.2.1製程條件 27
3.2.2量測參數 28
3.3實驗結果與討論 29
3.3.1使用不同Trimming時間方式在以氧化鉿為閘極介電層之SOI n-FinFET之等效電容電特性分析 29
3.3.2使用不同Trimming時間的方式在以氧化鉿為閘極介電層之SOI n-FinFET之電特性分析 30
3.3.3使用不同Trimming時間方式在以氧化鉿為閘極介電層之SOI n-FinFET之可靠度分析 34
3.3.4使用不同Trimming時間方式在氧化鉿作為高介電層在SOI n-FinFET電晶體元件之結構分析 36
3.4結論 37
第四章 不同高溫處理對於絕緣層覆矽鰭式電晶體之電性研究 52
4.1研究動機 52
4.2製程與量測 53
4.2.1製程條件 53
4.2.2量測參數 55
4.3實驗結果與討論 55
4.3.1不同高溫處理對SOI n-FinFET之等效電容電特性分析 55
4.3.2不同高溫處理對SOI n-FinFET之電特性分析 56
4.3.3 不同高溫處理對SOI n-FinFET之可靠度研究 60
4.3.4不同高溫處理對SOI n-FinFET之材料特性研究 60
4.4結論 61
第五章 結論與展望 76
5.1結論 76
5.2未來展望 77
參考文獻 78

[1] M. Agostinelli,VLSI Tech, p. 232, 2010.
[2] Dieter K. Schroder, “Semiconductor Material and Device Characterization”, third edition, 2006.
[3] J. H. Stathis, et al, IEEE IEDM, Vol. 71, p. 167, 1998.
[4] Yuan Taur, et al., First published 1998, Reprinted, p.161, 1999.
[5] D.C. Houghton, J. Appl. Phys, Vol. 70, p. 2136, 1991.
[6] M. Houssa, et al, Material Science and Enginerring R, p. 37, 2006.
[7] H. S. Momose, et al., IEEE Trans. Electron Devices, Vol. 43, p.1223, August 1996.
[8] S, Saito, et al., IEEE IEDM, p. 797, 2003.
[9] R. People , et al., Appl. Phys. Lett, Vol. 47, p. 322, 1985.
[10] Niraj K. Jha, Electrical Engineering, Princeton University.
[11] Hayashida et al., IEEE Trans. Electron Devices, Vol. 59, p. 647, March 2012.
[12] Georgios Vellianitis et al., IEEE IEEE Transactions on Electron Devices, Vol. 56, p.1548, No. 7, July 2009.
[13] C. Y. Kang, et al., IEEE International SOI Conference Proceedings, p. 135, 2006.
[14] Kang et al., IEEE Electron Device Letters, Vol. 29, p. 487, May 2008.
[15] M. Yang, in IEDM Tech. Dig. p. 453, 2003.
[16] C. Y. Kang, et al., IEEE IEDM, p. 1-, 2006.
[17] J.S. Lee, et al., IEEE Electron Device Letters., Vol. 24, p.186, 2003.
[18] S D Wang, et al.The Electrochemical Society, Vol. 152, G703-G706 , 2005.
[19] S. I. Takagi et al., IEEE Trans. Electron Devices, Vol. 41, no.12, p. 2357, 1994.
[20] T.P.Ma, IEEE Trans. Electron Device, Vol. 45, p. 680, March 1998.
[21] R. Woltjer, et al., IEEE Trans. Electron Devices, Vol. 42, p. 109, 1995
[22] Simulation bulk Inversion, Accumulation, Junctionless FinFET for TSMC 10nm and 7nm, 5nm nodes application, 2015.
[23] C. L. Lin, et al.,IEEE Transactions On Electron Devices, p. 3639, 2013.
[24] Tung Ming Pan, et al., Appl. Phys. Lett. Vol.78, p.1439, 2001.
[25] C. D. Young, et al., IEEE Device and Materail Reliability, Vol.6, p.123, 2006.
[26] Gareth Nicholson, et al., IEEE Electron Device Letters., Vol 28, p. 825, 2007.
[27] N. Collaert, et al. IEEE European Solid State Device Research Conference, p.143, 2007.
[28] B. D. Gaynor, et al.,IEEE Transactions On Electron Devices , p. 2738, 2014.
[29] Y. Cui, et al.,Nano Lett., Vol. 3,no. 2, p. 149, 2003.
[30] A. K. Sharma, et al.,Proc. Inst. Elect. Eng.—Circuits Device Syst., Vol. 151, no. 5, p. 422, Oct. 2004.
[31] S.-Y. Lee, et al.,IEEE Trans. Nanotechnol., Vol. 2, no. 4, p. 253, Dec. 2003.
[32] N. Singh, et al., IEEE Electron Device Letters., Vol. 27, p.383, May 2006.
[33] Weize Xiong, et al., IEEE Electron Device Letters, Vol. 25, p. 541, no. 8, August 2004.
[34] T. I. Kamins, et al.,IEEE Electron Device Letters, Vol. EDL-1, p. 159, no. 8, August 1980.
[35] I-Wei Wu, et al.,IEEE Electron Device Le'iters, Vol. 12, p. 181, no. 4, April 1991.
[36] N. H. Nickel, et al.,IEEE Transactions on Electron Devices, Vol. 42, p. 1559, no. 8, August 1995.
[37] D. Kaplan, et al.,Appl. Phys. Lett., Vol. 33, p. 440, September 1978.
[38] C. H. Seager, et al.,Appl. Phys. Lett., vol. 34, p. 337, March 1979.
[39] T. Makino, et al.,Appl. Phys. Lett.,Vol. 35, p. 551, October 1979.
[40] D. R. Campbell, et al. Appl. Phys. Lett., vol. 36, p. 604, April 1980.
[41] Nathan Willems, et al. IEEE International Conference on Nanotechnology., p.321, August 2013.
[42] 維基百科”https://zh.wikipedia.org/wiki/%E7%AD%89%E7%A6%BB%E5%AD%90
%E4%BD%93”.
[43] A Fontcuberta i Morral, et al. Non-Crystalline Solids, Vol. 299, p.196, 2002.
[44] 維基百科”https://zh.wikipedia.org/wiki/%E5%B0%96%E7%AB%AF%E6%94%BE%
E9%9B%BB”