本次實驗主要針對Silicide形成前的PAI (pre-Amorphous Implant)步驟進行討論，從文獻上得知，Silicide形成前的PAI步驟對於形成低阻值的C54 Ti Silicide有很大的幫助，而本次實驗主要分為兩個部分，第一部分以改變不同的PAI Profile討論元件阻值的改善，而第二部分則是以低溫環境下進行PAI製程討論元件漏電流的表現。透過使用HL-PAI Profile，可以得到大約15%整體阻值改善，而阻值改善可以歸納為下列三個因素，分別是1.) Silicidation形成中S/D Dopant Redistribution所造成的電子穿隧能障降低，2.) S/D中Si Vacancy殘留於表面對能帶的影響所導致得電子穿隧能障改變，和3.) S/D中不同Germanium含量對於低阻值的C54 Ti Silicide Formation Barrier大小的影響，而在飽和電流的改善上除了整體電阻降低的因素之外，從IV圖中也可以看到進行過HL-PAI的樣品電子遷移率有約8%的增益，綜合這兩因素，HL-PAI樣品飽和電流的改善大約12%左右。
第二部分的實驗中使用低溫PAI後的樣品在漏電流改善上非常的明顯，GIDL在I/O和core元件之間分別有3倍和1.5倍的改善，而Isoff (sub-Threshold Leakage) 和Junction Leakage於core元件中則分別有~2倍和~5倍的改善，這些漏電的改善可以歸因為S/D中EOR Defect在低溫PAI之下數量減少所致。

PAI (pre-Amorphous Implant) process before Ti Silicide formation have been discuss in this work, according to reference, PAI process which adopt before silicidation, improve low resistivity C54 Ti Silicide formation during sillicidation process. Two major topic have been discuss in this work.
First, different PAI profile have been used for resistance improvement, HL-PAI which have the promising performance, shows ~15% total resistance (RT) improvement in N-FinFET. It can be attribute to three different origin, leading to contact resistance (RC) reduction, which is the major component in RT. (1.) S/D dopant redistribution during silicidation, (2.) surface Si vacancy accumulation, resulting in electron tunneling barrier difference, and (3.) S/D Ge content caused C54 TiSi formation barrier difference. ~12% Saturation current improvement in N-FinFET HL-PAI sample can not only be attribute to following RT reduction, but electron mobility enhancement (~8%) observed in HL-PAI sample.
Second, cryogenic PAI sample shows significant leakage improvement against room temperature PAI sample, both 3 times and 1.5 time GIDL improvement can be seen for N-FinFET I/O and core device adopting cryo-PAI, also for N-FinFET core device ~2 times sub-threshold leakage (Isoff) and ~5 times junction leakage improvement can also been seen in cryo-PAI sample. These leakage improvement observed above might be attribute to EOR defect reduction by using cryo-PAI.

摘要 i
致謝 iii
目錄 iv
圖目錄 vi
表目錄 xi

第一章 序論 1
1-1背景介紹 1
1-2 Titanium Silicide Formation 2
1-3 Titanium Germanosilicide Formation with Different Ge Content 4
1-4 Introduction to Amorphous Layer Formation via Ion Implant 5
1-5 研究動機 8
1-6 論文結構 9
第二章 文獻回顧 21
2-1 1.5x10-9 Ω•cm2 Contact Resistivity on Highly Doped Si:P Using Ge Pre-amorphization and Ti Silicidation 21
2-2 Ultra Low p-Type SiGe Contact Resistance FinFETs with Ti Silicide Liner using Cryogenic Contact Implantation Amorphization and Solid-Phase Epitaxial Regrowth (SPER) 22
第三章 實驗流程 31
3-1 元件製程 31
[第一部分] 不同濃度的鍺濃度分布對於接面電阻之影響 32
[第二部分] 低溫離子佈植對元件特性之影響 33
3-2 元件量測 33
第四章 結果與討論 41
[第一部分] 不同濃度的鍺濃度分布對於接面電阻之影響 41
4-1 阻值改善和相關電性表現 41
4-2 N/P-FinFET元件特性表現 44
[第二部分] 低溫離子佈植對接面電阻之影響 60
4-3 阻值改善和相關電性表現 60
4-4低溫離子佈值對FinFET元件漏電流改善 62
第五章 結論與未來展望 70
參考文獻 71

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