CoWoS (Chip-on-Wafer-on-Substrate ) :，採用矽穿孔(through-silicon vias, TSVs)的矽晶圓當作載具，在單一元件中整合數枚晶片以減低功耗、改善系統特性以及縮小物件尺寸。先以CoW技術將矽晶片連接到經過TSV處理的晶圓後，再將這個次系統附著到基板上以組成最後的元件(oS) 。
CoWoS晶片必須透過Pick and Place (PnP) 將不同 Chip整合到Substrate 上，是最關鍵的技術，也是Bottleneck 。改善
本論文即為探論建構新產能時，機台的purchase spec決策分析。

With the absent of the end of Moore’s Law, all semiconductor foundries are working on another way to break through the physics limitation. All this efforts such as MEMS, Ultra-Low-Power IC, Mixed Signal IC and 3D-IC etc are called “More-than-Moore.” Among More-than-Moore, the most likely solution to extend Moore’s Law is the 3D-IC technology. As a core process of 3D-IC, Pick & Place process (P&P) is getting more and more important and being expected to have more powerful function nowadays. Traditionally in prior art, tool only allows 10 configurations to select and re-arrange
different bin codes, but the customer usually have more than 10 configurations on each order. As a result of that, manually revising bin configurations during an order is needed. That causes the automation of equipment to be limited. Another issue is for the next generation 3D-IC based GPU, DRAM and GPU have to do P&P in the same stage in order to cost down. DRAM likely comes from Tape & Reel (T&R) or Film Frame (FF) packages, and GPU comes from film frame package (but with 2 different types.) The above complexity causes P&P process manually, low WPH, high MO risk and high CoO. We developed an all in one die bonder as a solution, it merges T&R, 2 types of film frame process in the same time and it’s automatically, high WPH, no MO risk and lower CoO. Moreover, it supports bin configurations to be controlled by each substrate to solve the 10 configuration limitation and to achieve the real automation.

1.Introduction/ Purpose..... 1
2.Literature survey......... 6
3.Study Architecture........ 8
4.Empirical Study........... 11
5.Conclusion................ 17
Reference................... 18

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