本論文中，首先完成了一個應用在Ku頻段低雜訊降頻器之鎖相迴路，並介紹二個與其相關的Class-C壓控震盪器設計。第二部分介紹二個採用不同架構的高解析度時間數位轉換器，其中採用全新設計的免校正式時間放大器，以達到低於1ps的時間解析度。最後一部分則完成了一個可程式化主動式時間偏移器電路，應用在全雙工收發機之類比自我干擾消除電路中，提供其中所需的時間間隔。本論文中所有電路皆在TSMC 90奈米CMOS製程中下線實作。
第一個Class-C壓控震盪器採用推拉式架構以及變壓器偏壓技巧，量測到在1 MHz偏移下的最佳相位雜訊為-121 dBc/Hz，達到的FoM值為190 dBc/Hz。第二個Class-C壓控震盪器被使用在鎖相迴路之中，採用傳統架構加上數位調控式電容陣列以增加調整頻寬。在鎖相迴路的部分輸出需符合DVB-S和ABS-S規格，涵蓋9.75 GHz、10.6 GHz、10.75 GHz和11.3 GHz等四個頻率，採用了上述數位頻段控制式壓控震盪器，此鎖相迴路可順利在此四頻率中鎖定。
在時間數位轉換器的部分，我們提出了具高線性度的免校正式時間放大器架構，首先使用在一個9位元4級式時間數位轉換器電路中，在量測中可達到0.86ps時間解析度，但因為受到隨機偏移量的影響，量測出的線性度較模擬結果差了許多。在第二個設計中採用了常見的1.5位元循環式架構以增加強韌度，實現了一個9位元循環式時間數位轉換器，在模擬中同樣達到了0.86ps的時間解析度，並且伴隨著面積減少的優點。此外，儘管此電路尚在晶圓廠製作中，我們仍可預期量測結果會和模擬更為接近。
最後則介紹了可程式化主動式時間偏移器，採用gm-C全通式濾波器作為時間偏移地逼近方式。本電路含有五位元數位編碼，可控制約為10ps的延遲間隔，涵蓋5.8 GHz干擾消除電路所需延遲量。最後得到的group delay範圍從100ps直到370ps，並在1 GHz頻寬內最大偏移量約為10ps，其平坦度相當足夠。

This thesis presents an integer-N phase-locked loop (PLL) for Ku-band low-noise block (LNB) downconverter in satellite communication systems along with two class-C voltage controlled oscillators (VCOs), two high resolution time-to-digital converters (TDCs) utilizing a novel calibration-free time amplifier, and an active programmable time shifter for 5.8 GHz full-duplex radio analog echo cancellation (AEC) circuit. All the presented circuits are fabricated in TSMC 90nm CMOS process.
The first class-C VCO is designed with push-pull topology with a transformer biasing technique. Fabricated in TSMC 90nm CMOS process, the VCO achieves a phase noise of -121 dBc/Hz at 1MHz offset with an FoM up to 190 dBc/Hz. The second class-C VCO which is used in the PLL follows the conventional topology, and a digital-controlled capacitor bank is added to widen the frequency tuning range. The PLL is designed to cover four frequencies for both DVB-S and ABS-S standards, including 9.75 GHz, 10.6 GHz, 10.75 GHz, and 11.3 GHz. Using the second class-C VCO with digital band control, the PLL can be successfully locked in these four frequencies.
We also propose a novel calibration-free time amplifier for high resolution TDCs, which is the most critical block in multi-step TDC topologies. With the time amplifier, the designed 9-bit four-stage TDC has achieved a desired time resolution of 0.86 ps in measurements, but the linearity is not as good as the simulated results due to offsets. In the second TDC design, the popular 1.5-bit cyclic structure is introduced to improve robustness of the TDC. The proposed 9-bit cyclic TDC has the advantage of area reduction with a similar simulated resolution of 0.86ps. Although the circuit is still under fabrication, we expect the measured results will be closer to simulation compared with the previous design.
The last circuit introduced in this thesis is a programmable active time shifter, which uses the gm-C all-pass filter to approximate a true time delay transfer function. The proposed structure consists five digital control bits with a group delay step about 10 ps, which can cover the desired time step for 5.8 GHz AEC circuit. The group delay ranges from 100 ps to 370 ps at 5.8 GHz, and the maximum group delay discrepancy over a GHz bandwidth is only about 10 ps, which shows a sufficient flatness.

摘要 i
ABSTRACT ii
TABLE OF CONTENTS iv
LIST OF FIGURES vii
LIST OF TABLES xii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
Chapter 2 Design of Ku-Band PLL for LNB Downconverter with Class-C Voltage-Controlled Oscillators 4
2.1 Basic LC Oscillators 4
2.1.1 LC tank 4
2.1.2 Cross-Coupled Pair 6
2.2 Phase Noise of an LC Oscillator 7
2.2.1 Phase and Amplitude Noise 8
2.2.2 Hajimiri’s Phase Noise Model 8
2.2.3 Effective ISF 12
2.2.4 Class-C VCO 13
2.3 Design of a Push-Pull Class-C VCO 15
2.3.1 Concepts of Push-Pull Class-C VCO 15
2.3.2 Proposed Class-C VCO with Transformer Biasing 16
2.3.3 Experimental Results 18
2.3.4 Comparison and Summary 20
2.4 Basic Concepts of Phase-Locked Loop 22
2.4.1 Charge pump PLL 22
2.4.2 Linear Model 22
2.4.3 Phase Noise of PLL 23
2.5 Ku-Band PLL for LNB downconverters 25
2.6 Design of PLL Sub-Circuits 26
2.6.1 TSPC Phase/Frequency Detector 26
2.6.2 Current-Matched Charge Pump 27
2.6.3 Current Mode Logic (CML) Divider 28
2.6.4 Enhanced TSPC Modular Programmable Divider 29
2.7 Class-C VCO with Digital Band Tuning 31
2.7.1 Digital-Controlled Capacitor Bank 32
2.7.2 Optimization of LC Components 34
2.7.3 Simulation Results 35
2.8 Complete Ku-band PLL 36
2.9 Experimental Results 38
2.10 Comparison and Summary 41
Chapter 3 Design of High Resolution Multi-Stage and Cyclic Time to Digital Converters 42
3.1 Basic Concepts of Time-to-Digital Converters 42
3.2 Popular Topologies of TDCs 43
3.2.1 Delay-Line TDCs 43
3.2.2 Vernier Delay-Line TDCs 44
3.2.3 Gated Ring Oscillator TDC 44
3.2.4 Stochastic TDC 46
3.2.5 Coarse-Fine TDC 48
3.2.6 Pipeline TDC 49
3.2.7 Cyclic TDC 51
3.3 Time Amplifiers 52
3.3.1 Design with Metastability 52
3.3.2 Pulse Train Time Amplifier 55
3.3.3 The Proposed Time Additive Time Amplifier 56
3.4 Design of the Proposed Four-Stage TDC 58
3.4.1 Block Diagram 58
3.4.2 Time Arbiter 59
3.4.3 2-bit TDC Stage 61
3.4.4 Time Amplifier 62
3.5 Experimental Results of the Four-Stage TDC 65
3.5.1 Simulation Results 65
3.5.2 Measurement Results 67
3.5.3 Discussion and Summary 70
3.6 Design of the Proposed Cyclic TDC 73
3.6.1 Design Target and General Modification 73
3.6.2 Block Diagram 74
3.6.3 1.5-Bit MTDC 75
3.6.4 Simulation Results 79
3.7 Summary 84
Chapter 4 Design of an Active Time Shifter for a 5.8 GHz Full-Duplex Radio Transceiver 85
4.1 Concepts of Full-Duplex Radio 85
4.2 Active True Time Delay Line 87
4.3 Programmable Delay-Line Based on gm-C APF 89
4.4 Experimental Results 93
4.5 Summary and Comparison 97
Chapter 5 Conclusions and Future Works 99
References 101

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