近年來，隨著半導體製程技術不斷的進步，金氧半場效電晶體(MOSFET)元件尺寸不斷微縮。鰭式場效電晶體(FinField-effect transistor, FinFET)被視為在20nm製程下主要的解決方法。
然而在先進CMOS製程中，精確地控制3D結構是達成奈米微縮(nano-scale)中最重要的挑戰。閘極氧化層厚度隨著微縮製程越來越薄，氧化層與高介電材料/金屬閘可靠度也是微縮製程的重點之一。傳統的電漿感應電荷偵測器通常包含一個連接在天線上的電晶體閘極用於反應電荷效應。再利用不同的測量機制揭露天線閘極電晶體的潛在氧化損害程度，機制如掃描電壓(ramp voltage)或定電壓加壓測試(CVS)、定電流加壓測試(CCS)。崩潰電壓、電荷捕捉速率和加壓下的時間相依測量都可以用於揭露氧化損害程度。然而，這些測試可能會非常耗時，沒辦法提供製程監測與製程實時回饋。除此之外，在電漿感應電荷期間之極性與非均勻性都無法透過傳統測試方式明確定義。
因此在此篇論文，我們利用FinFET製程提出了一個新型的結構應用於監測與紀錄晶圓的電漿感應電荷。此晶圓上的電荷收集器擁有天線耦合浮動閘極，吸引基底之電荷進入浮動閘極，可以成功地記錄在後端(back-end-of-the-line, BEOL)製程上電漿電荷的程度。量測之截止電壓可以回推至浮動閘極電荷和電場，最後可預測出作用於電晶體閘極上真實的電壓分佈，對於未來的FinFET製程最佳化和可靠性評估有極大的幫助。

Recently, as semiconductor process technology continually advances, the scaling of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has been continuing. Fin-shaped field effect transistors (FinFETs) are considered as the main solution for process beyond 20nm technology nodes.
However, precision control of 3D structures is one of the most important challenges to the success of advanced nano-scale CMOS technologies. Gate oxide thickness decreases for technology process scaling. The reliability of gate oxide and high-k material/metal gate is one of the most important thing of process scaling. Traditional PID (plasma induced damage) monitoring devices usually has a transistor gate connected to large antenna structures, which can reflect the charging effect. Many measuring schemes have been used to reveal the latent oxide damage level in antenna gate transistors, such as ramp breakdown test or constant voltage/current stress (CVS or CCS) measurement. Other measurements, such as breakdown voltage, charge trapping rate, and time-to-breakdown measured under stress can reveal latent oxide damage levels. However, traditional tests can be very time consuming, and cannot provide the real-time feedback for process monitoring. In addition, the polarity and non-uniformity of charging effect during PID cannot be defined by traditional measurements.
Therefore, in this research, we propose a novel structure for PID monitoring, which can reveal the wafer-level plasma-induced charging effect in advanced FinFET processes. The structure consists of antenna-coupled floating gates, which can abstract the charge tunneling from the substrate and successfully record the plasma charging levels during BEOL process. The measured threshold voltage distribution can estimate to floating gate charge and electrical field. Finally, the actual potential distribution on the transistor gates can be projected by the positive and negative charging effects on the floating gates, provides a powerful tool for future FinFET process optimization and reliability evaluations.

摘要…….. i
Abstract…. ii
致謝…….. iv
內文目錄.. v
附圖目錄.. vii
附表目錄.. x
第一章 序論 1
1.1 天線效應簡介 1
1.2 研究動機 3
1.3 論文大綱 4
第二章 天線效應偵測方法回顧與發展 8
2.1 電漿充電損害效應 8
2.2 傳統PID偵測之分析方法 9
2.2.1 時間相依介電質崩潰測試 (TDDB) 9
2.2.2掃描崩潰電壓測試 (Ramp Breakdown Voltage) 10
2.2.3電容-電壓測試 (C-V) 11
2.2.4閘極漏電流測試 (Gate Leakage Current) 12
2.2.5電壓-時間測試 (IETR) 12
2.2.6電子抹除式可複寫唯讀記憶體(EEPROM)偵測器 13
2.3 小結 14
第三章 天線效應記錄元件介紹與操作機制 24
3.1 元件結構與製程介紹 25
3.1.1 元件結構 25
3.1.2 製程介紹 26
3.2 載子注入機制回顧 27
3.2.1 穿隧效應 (Fowler-Nordheim, FN) 27
3.2.2 通道熱電子注入機制 (Chanel Hot Electron ,CHE) 28
3.3 元件操作機制及耦合結構設計 29
3.4 小結 30
第四章 天線效應記錄元件量測與分析 39
4.1 量測裝置及機台設定 39
4.2 基本特性量測與天線設計 39
4.3 不同金屬層之PID分布 42
4.4 天線與浮動閘極耦合程度之影響 43
4.5 正負電荷之分佈 44
4.6 資料儲存性 45
4.7 小結 45
第五章 總結 68
5.1 元件與現行偵測方法之比較 68
5.2 結語與未來展望 69
參考文獻 71

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