隨著資料傳輸的速度越來越高，傳統的銅導線將面臨其高損耗與高串音(cross talk)的物理極限。然而，光纖具有高頻寬、低損耗、低電磁干擾與低串音等特性，非常適合應用於高速傳輸的介面。近年來，高速光通訊傳輸除了傳統的骨幹網路(backbone)以外，也逐漸導入消費性電子產品的應用，例如USB及HDMI等介面。此外，在雲端的應用日漸蓬勃之際，資料中心(Data center)也大幅以光通訊作為其伺服器之間資料交換的主要技術。因此，光纖通訊未來的成長與應用是可以被預期的。
第二章中，將會介紹一個操作於10-Gb/s 的轉阻放大器與限制放大器的共同設計實現於90 nm CMOS 製程中。利用RGC架構當作轉阻放大器輸入級，可得到一較低的輸入阻抗而提升整體頻寬。使用一些增益峰化的技術，可以使得限制放大器獲得一高增益與高頻寬的特性。因此在1.5 V操作電壓下，可得到整體85 dBΩ的轉阻增益、9.6 GHz的頻寬、130 mW的功率消耗與0.59 mm2的晶片面積。
第三章中，40-Gb/s的轉阻放大器被實現於90 nm CMOS 製程中，此電路利用一改善的RGC架構當作其輸入級，並且利用一些電感的峰化技術來提升整體頻寬，使得電路可以操作於低的操作電壓。在0.8 V操作電壓下，可以得到50 dBΩ轉阻增益、24 GHz頻寬、6.7 mW功率消耗與0.31 mm2的晶片面積。
第四章中，兩個40-Gb/s的轉阻放大器被實現於90 nm CMOS 製程中。第一個電路利用一改善的RGC架構當作其輸入級，並且利用Reversed triple resonance network (RTRN)的技術來提升整體頻寬，使得電路可以操作於低的操作電壓。並且利用三維(3D)的技術來實現電感，大幅減低晶片面積。在0.8 V操作電壓下，可以得到50.3 dBΩ轉阻增益、29.6 GHz頻寬、7.6 mW功率消耗與0.23 mm2的晶片面積。第二個電路利用共閘極架構當作其輸入級，同樣利用Reversed triple resonance network (RTRN)的技術來提升整體頻寬，使得電路可以操作於低的操作電壓。並且利用三維(3-D)的技術來實現電感，大幅減低晶片面積。此架構將比RGC輸入級的架構擁有更高的頻寬、更低的輸入參考雜訊與更低的功率消耗。在0.8 V操作電壓下，可以得到50 dBΩ轉阻增益、30.8 GHz頻寬、4.1 mW功率消耗與0.23 mm2的晶片面積。
在第五章中，將會給予上述電路設計的結論以及未來的工作。

As the speed of data transmission keeps increasing, traditional copper wire reaches its physical limit, including high loss and high cross talk. In contrast, optical fiber has the characteristics of high bandwidth, low loss, low EMI and low cross talk, which is very suitable for the applications of high speed communications. In recent years, in addition to traditional backbone network, high speed optical communication is gradually applied for commercial electronics products such as USB and HDMI interfaces. Besides, due to the flourishing applications of cloud computing, data centers substantially adopt optical communication as the main technology for data transmission among the servers. Therefore, the future growth and applications of optical communication are expected.
In chapter 2, we will introduce a co-design of transimpedance amplifier and limiting amplifier operated at 10-Gb/s in 90 nm CMOS. Using the topology of regulated cascode (RGC) as the input stage of the transimpedance amplifier, a low input impedance can be obtained thus the bandwidth can be enhanced. Using the design techniques of gain peaking, the limiting amplifier can obtain characteristics of high gain and high bandwidth. Under a supply voltage of 1.5 V, 85 dBΩ transimpedance gain and 9.6 GHz bandwidth are achieved with 130 mW power consumption and a 0.59 mm2 chip area.
In chapter 3, a 40-Gb/s transimpedance amplifier is realized in 90 nm CMOS. It adopts a modified regulated cascode (RGC) as input stage and the techniques of inductor peaking for bandwidth improvement thus it can operate at a low supply voltage. Under a supply voltage of 0.8 V, 50 dBΩ transimpedance gain and 24 GHz bandwidth are achieved with 6.7 mW power consumption and a 0.31 mm2 chip area.
In chapter 4, two 40-Gb/s transimpedance amplifiers are realized in 90 nm CMOS. The first one adopts a modified regulated cascode (RGC) as input stage and the technique of reversed triple resonance network (RTRN) for bandwidth enhancement thus it can operate at a low supply voltage. Besides, using the technique of three-dimensional inductors, the chip area is substantially reduced. Under a supply voltage of 0.8 V, it can obtain a 50.3 dBΩ transimpedance gain, 29.6 GHz bandwidth with 7.6 mW power consumption and a 0.23 mm2 chip area. The second design uses a common-gate configuration as the input stage and the technique of reversed triple resonance network (RTRN) for bandwidth enhancement and low voltage operation. Similarly, the chip area is substantially reduced by using 3-D inductor. This topology leads to a higher bandwidth, lower input-referred noise and lower power consumption than the RGC input stage. Under a supply voltage of 0.8 V, it can obtain a 50 dBΩ transimpedance gain, 30.8 GHz bandwidth, 4.1 mW power consumption and 0.23 mm2 chip area.
In chapter 5, we will give the conclusions with the recommendation of future works.

ABSTRACT i
摘要 iii
CONTENTS v
LIST OF FIGURES & TABLES viii
CHAPTER 1 1
INTRODUCTION 1
1.1 Background and Motivation 1
1.2 Thesis Organization 2
CHAPTER 2 4
A 10-Gb/S TRANSIMPEDANCE AMPLIFIER AND LIMITING AMPLIFIER CO-DESIGN IN 90 NM CMOS 4
2.1 Introduction to Transimpedance Amplifier 4
2.1.1 Specifications of Transimpedance Amplifier 4
2.1.2 Common topologies of transimpedance amplifier 6
2.2 Bandwidth Extension Techniques 11
2.2.1 Shunt Inductive Peaking 11
2.2.2 Asymmetric T-coil Peaking 12
2.2.3 π- type Inductor Peaking 13
2.3 Introduction to Limiting Amplifier 14
2.3.1 Specifications of Limiting Amplifier 14
2.3.2 Design Analysis of Limiting Amplifier 16
2.3.3 Bandwidth Analysis of Limiting Amplifier 18
2.4 Proposed Circuits 19
2.4.1 Proposed Transimpedance Amplifier 19
2.4.2 Proposed Limiting Amplifier 21
2.5 Simulated and Measured Results 27
2.5.1 Frequency Domain 27
2.5.2 Time Domain 30
2.6 Summary and Conclusion 32
CHAPTER 3 34
A 40-Gb/S TRANSIMPEDANCE AMPLIFIER WITH LOW POWER CONSUMPTION IN 90 NM CMOS 34
3.1 Proposed Transimpedance Amplifier 34
3.2 Simulated and Measured Results 41
3.2.1 Frequency Domain 41
3.2.2 Time Domain 43
3.3 Summary and Conclusion 47
CHAPTER 4 49
40-Gb/S LOW POWER TRANSIMPEDANCE AMPLIFIERS WITH RTRN TECHNIQUE AND 3D INDUCTOR IN 90 NM CMOS 49
4.1 Proposed Transimpedance Amplifiers 49
4.2 Design of 3-D Inductor 56
4.3 Simulated and Measured Results 59
4.3.1 Frequency Domain 59
4.3.2 Time Domain 61
4.4 Summary and Conclusion 65
CHAPTER 5 67
CONCLUSIONS AND FUTURE WORKS 67
REFERENCES 69

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