此論文中，完成了兩個實作在0.18-um BiCMOS製程之接收機，分別應用於Ku頻段(10.7~13.45GHz)與Ka頻段(18.2~22.2GHz)。主要探討應用於低雜訊降頻器(Low noise block)系統之寬頻低雜訊接收機的電路設計、模擬與量測，其中電路架構包含了三個部分，分別是低雜訊放大器(LNA)、混頻器(Mixer)與中頻放大器(IFA)。
於Ku頻段應用中，LNA在輸入端使用變壓器回授匹配網路的方式，同時達成寬頻阻抗匹配與低雜訊的特性。混頻器部分使用改良式吉爾博式架構(Gilbert Mixer)，在輸入端使用被動式平衡器(passive balun)單端轉雙端，以達到低雜訊與低功耗設計。之後接了一個雙端轉單端的主動式鏡像電路，並使用電容退化技術來提升頻寬。中頻放大器(IFA)使用gm3 補償技術與3D電感技術來增加頻寬與線性度。
於Ka頻段應用中，中頻部分電路與Ku頻段的設計相同。不同處在於此LNA改良Ku頻段的設計，在第一級負載端與第二級源極端使用變壓器回授以提升頻寬與雜訊匹配。混頻器部分使用電路注入式架構提升增益與降低雜訊。兩顆射頻前端電路的增益有45dB以上、雜訊在7dB以下和線性度OP1dB也約有+4dB，皆符合計畫需求。
此論文也完成了一個90-nm CMOS製程之功率放大器，應用於C頻段(4~8GHz)中，使用兩級cascode的架構提供高增益，此電路包含了一級推動級、一級功率級以及三個被動式變壓器式的匹配網路，將負載阻抗匹配置最佳阻抗點。達成4~8GHz的寬頻、增益大於30dB、輸出功率OP1dB為14dBm和功率增進效率(PAE)為20%的設計。

This thesis presents two RF front-end receivers in 0.18 um BiCMOS for Ku-band (10.7~13.45GHz) and Ka-band (18.2~22.2GHz) applications, respectively. This thesis discusses the wideband low-noise receiver for low-noise block design regarding the circuit designs, simulations and measurements. The circuit topologies include three parts about low-noise amplifier (LNA), down conversion mixer and intermediate frequency amplifier respectively (IFA).
For Ku-band applications, the input matching network of LNA is designed by transformer to achieve wideband matching and low noise operation simultaneously. The mixer of frond-end receiver used the improved Gilbert-based mixer with a passive balun to accomplish single-ended to differential conversion between the transconductance stage and switch stage. It achieves low noise and low power consumption. Next stage uses the active current mirror circuit to convert differential to single-ended and also uses capacitor degeneration technique to enhance the overall bandwidth. Last stage, IFA, uses gm3 compensation technique and 3D inductor to increase the bandwidth and linearity.
For Ka-band application, the design of intermediate frequency part is similar with our previous work at Ku-band. For LNA circuit, the gate-to-source transformer feedback matching network with external capacitor CEXT is used to achieve the wideband power matching and reduce the noise figure. The mixer of receiver front-end uses the Gm-boosted current bleeding structure to improve gain and noise performance. Both RF front-ended receivers achieve conversion gain of 45dB, the noise figure is smaller than 7dB and the linearity OP1dB is above 4dBm.
In addition, this thesis also presents a wideband transformer-based power amplifier in 90-nm CMOS process for C-band (4~8GHz) applications. By utilizing a two-stage cascade structure, the high gain performance can be obtained. The circuit schematic consists of a driver stage, a power stage, and three matching network by transformer at the input, interstage, and output for matching the maximum power matching impedances of the power and driver stage. The PA achieves a 3-dB bandwidth in a range of 4~8GHz, gain about 30dB, OP1-dB of 14dBm and power-added-efficiency of 20%.

致謝 ii
摘要 iii
Abstract iv
Contents vi
List of Figures viii
List of Table xiii
Chapter 1 Introduction 1
1.1 Motivation for Satellite Receiver 1
1.2 Motivation for Power Amplifier 3
1.3 Thesis Organization 5
Chapter 2 Fundamentals for Receiver and Power Amplifier 6
2.1 Basics of Low Noise Amplifier Design 7
2.2 Basics of Mixer Design 12
2.3 Basics of Power Amplifier Design 20
2.4 Summary 27
Chapter 3 High-Gain Receiver Front-end for Ku-band Satellite TV Applications 28
3.1 LNA using TF Feedback Technique 28
3.2 TF-Based Down Conversion Mixer 34
3.3 Buffer with Degeneration Capacitor 37
3.4 IFA with gm3 Compensation and 3D Inductor 39
3.5 Circuit Schematic and Measured Results 44
3.6 Summary and conclusion 48
Chapter 4 High-Gain Receiver Front-end for Ka-band Satellite TV Applications 49
4.1 Dual-Transformer-Feedback LNA 50
4.2 Invertor-Typed Current Bleeding Mixer 52
4.3 Circuit Schematic and Measured Results 55
4.4 Summary and Conclusion 59
Chapter 5 A High Efficiency Wideband Power Amplifier in 90nm CMOS 60
5.1 Design of a Power Transistor Cell 60
5.2 Design of the Transformer 62
5.3 Design of TF Matching Network 65
5.4 Circuit Schematic & Measured results 68
5.5 Summary and Conclusion 74
Chapter 6 Conclusion and Future Work 75

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