近十年來，半導體產業跟隨著摩爾定理的預測，元件尺寸持續微縮，而為了克服漏電或電流大小等問題，研究人員發想了各種新的結構以及製程。在20奈米以下的邏輯製程，有別於以往的平面型結構，改為立體型閘極包覆之形狀。此結構藉由物理方式去使空乏區域能完整的環繞著基底，使其空乏區漏電大幅降低，且提高閘極控制能力，而達到繼續微縮製程之目的。
而隨著閘極介電層的厚度降低，過往的天線效應(Antenna Effect)偵測方式需要改變。以前可以藉由設計大面積之金屬板連接至閘極，觀察電晶體之次臨界擺幅(Subthreshold Swing)、臨界電壓(Threshold Voltage)、依時性介電層崩潰測試(Time Dependent Dielectric Breakdown, TDDB)等等之變化，藉由這些參數去定量天線效應影響之程度。或是藉由一些量測方式去偵測天線效應造成之損害，如電容-電壓量測、閘極漏電流量測等方式去探討，但隨著氧化層厚度降低，由於FN穿隧電流會直接流過氧化層，使得天線效應對於閘極氧化層的影響無法利用電晶體的參數快速得知其受損情形，且無法量化受損程度，因此需要其他方法偵測。
而在此篇論文，提出了一個接觸槽耦合浮動閘極之結構，利用耦合電壓方式去傳遞電漿製程時產生的高電壓至浮動閘極，吸引基底之電荷進入浮動閘極。因此我們可利用此特性將電荷儲存在浮動閘極，使我們能定量且定性的分析電漿充電損害的嚴重程度。此元件可作為在晶圓生產時的測試圖樣，置放於晶圓的不同位置，並連接至不同層之金屬層，可即時的讓人員藉由簡易的電性量測影響較嚴重的金屬層位置，可迅速的聚焦電漿損害發生原因，對於良率提升以及損害來源之分析有很大的幫助。

Semiconductor manufacturing technology has followed the prediction of Moore’s Law in past decades, and the size of transistors scaled down continually. To overcome the issue of leakage current and the on current level, researchers come up with new structures and process method. In the CMOS logic process under 20nm, we change to 3D structure which has gate covering the fin. We can make the depletion region fully surround the substrate in FinFET structure, and this design leads to low leakage current and excellent gate control. It is advantage to scale down the device.
When the thickness of gate dielectric scales down, the method to detect the antenna effect needs to be changed. We can connect the gate to metal layer which has big area, and observe the subthreshold swing, threshold voltage, transconductance and TDDB results of the transistor. And we can use these parameters to detect the influences of antenna effect. Also, we can use some measurement skills to detect the plasma induced damage. For example, C-V measurement, gate leakage current measurement. But as the dielectric thickness scales down, the FN leakage current will go through the dielectric directly, and the damage will not show in the parameters of transistor, and we will underestimate the damage due to antenna effect. So we need another methods or devices to trace the plasma induced damage.
In this paper, we propose a structure using contact coupling floating gate, and we use it to pass the high voltage to floating gate to attract the charges from substrate in the plasma process. We can store the charges in the floating gate and quantitatively and qualitatively analyze the damage due to plasma charging. This device can be used as the test pattern on the wafer in the processes. We can put it on the different locations and connect it to different metal layers. Researchers can detect the damage on time and focus on the issue by simple measurement. It will help a lot in the process of wafer.

摘要 i
Abstract ii
致謝 iv
內文目錄 v
附圖目錄 vii
附表目錄 ix
第一章 序論 1
1.1 天線效應簡介 1
1.2 研究動機 3
1.3 論文大綱 4
第二章 天線效應偵測方法回顧與發展 6
2.1 臨界電壓、電導、次臨界擺幅特性參數偵測 6
2.2 氧化層崩潰所需電荷測試(QBD) 7
2.3 電壓-時間測試(IETR) 7
2.4 閘極漏電流測試(Gate Leakage Current) 8
2.5 電容-電壓測試(C-V) 8
2.6 掃描崩潰電壓測試(Ramp Breakdown Voltage) 8
2.7 EEPROM偵測器 9
2.8 小結 10
第三章 天線效應偵測元件介紹與操作機制簡介 18
3.1 元件結構與製程介紹 18
3.1.1 元件結構 18
3.1.2 製程介紹 19
3.2 載子注入機制回顧 21
3.2.1 Fowler-Nordheim(FN) 穿隧效應 21
3.2.2 通道熱電子注入機制(Chanel Hot Electron, CHE) 21
3.3 浮動閘極寄生電容 23
3.4 操作原理 23
3.5 小結 24
第四章 天線效應偵測元件量測與分析 33
4.1 量測環境 33
4.2 基本特性量測分析 33
4.3 不同天線參數之影響(面積、金屬層位置) 34
4.4 不同耦合程度之影響 35
4.5 其他電壓耦合方式 36
4.6 晶圓位置之變異性 36
4.7 資料儲存性 38
4.8 薄氧化層之影響 38
4.9 小結 39
第五章 總結 62
5.1 元件與現行偵測方法之比較 62
5.2 結語與未來展望 63
參考文獻 65

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