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[1] R.A. Bheda, J.A. Poovey, J.G. Beu, and T.M. Conte, “Energy Efficient Phase Change Memory Based Main Memory for Future High Performance Systems” , in IGCC, Washington, pp.1-8, 2011. [2] R. E. Simpson, P. Fons, A. V. Kolobov, T. Fukaya, M. Krbal, T. Yagi and J. Tominaga, “Interfacial phase-change memory”, in Nature nanotechnology, pp.501-505, Jul 2011. [3] J.C. Slonczewski, “Current-driven excitation of magnetic multilayers”, in Journal of Magnetism and Magnetic Materials, vol.159, pp.L1-L7, Jun. 1996. [4] C.J. Lin, S.H. Kang, Y.J. Wang, K. Lee, X. Zhu, W.C. Chen, X. Li, W.N. Hsu,Y.C. Kao, M.T. Liu, W.C. Chen, Y.Lin, M. Nowak, N. Yu and L. Tran, ” 45nm Low Power CMOS Logic Compatible Embedded STT MRAM Utilizing a Reverse-Connection 1T/1MTJ Cell”, in IEDM, Baltimore, pp.1-4, Dec. 2009. [5] C.Y. Lin, D.-Y. Lee, C.C. Lina, and T.Y. Tseng ,“Effect of thermal treatment on resistive switching characteristics in Pt/Ti/Al2O3/Pt devices”,in Surface Coatings Technol.,vol. 203, pp. 628–631, Dec .2008. [6] I.S. Park, K.R. Kim, S. Lee and J. Ahn,”Resistance switching characteristics fornonvolatile memory operation of binarymetal oxides”, in Jpn. J. Appl. Phys., vol. 46,pp. 2172–2174, Apr. 2007. [7] D. S. Jeong , z. Schroeder, and R. Waser,”Coexistence of bipolar and unipolar resistiveswitching behaviors in a Pt/TiO2/Ptstack”, in Electrochem Solid-State Lett., vol. 10,pp. G51–G53, 2007 [8] K.P. Chang,W.C. Chien,Y.C. Chen,E.K. Lai, S.C.g Tsai,S.H. Hsieh,Y.D.Yao,J. Gong;K.Y. Hsieh,R. Liu and C.Y. Lu, “Low-voltage and fast-speed forming processof tungsten oxide resistive memory,” in Extended Abstracts Int. Conf. Solid State Devices Mater., Tsukuba ,pp. 1168–1169, Sep .2008. [9] Y.W. Chin, S.E.Chen, M.C. Hsieh, T.S. Chang, C.J. Lin, Y.C. King, “Point twin-bit RRAM in 3D interweaved cross-point array by Cu BEOL process”, in IEDM, Dec. 2014. [10] M.C Hsieh, Y.C. Liao, Y.W. Chin, C.H. Lien, T.S. Chang, Y.D. Chih, Natarajan S, M.J.Tsai, Y.C. King, C.J. Lin, “Ultra high density 3D via RRAM in pure 28nm CMOS process”, in IEDM, Dec. 2013. [11] W.C. Shen, C.Y. Mei, Y.D. Chih, S.S. Sheu, M.J. Tsai, Y.C. King, C.J. Lin, “High-K metal gate contact RRAM (CRRAM) in pure 28nm CMOS logic process”, in IEDM, Dec. 2012 [12] Y. Watanabe, J. G. Bednorz, A. Bietsch, Ch. Gerber, D. Widmer, A. Beck, and S. J. Wind, “Current-driven insulator-conductor transition and nonvolatile memory in chromium-doped SrTiO3 single crystals”, in Appl. Phys. Lett., vol.78, pp.3738–3740, 2001. [13] A.Beck, J.G. Bednorz, C. Gerber, C. Rossel, D. Widmer, ”Reproducible swiching effect in thin oxide films for memory applications”, in Appl. Phys. Lett., 2000. [14] C. Cagli, D. Ielmini, F. Nardi and A. L. Lacaita, “Evidence for threshold switching in the set process of NiO-based RRAM and physical modeling for set, reset, retention and disturb prediction”, in IEDM, pp.1-4, 2008. [15] S. Yu, H.-S. Philip Wong, “Compact Modeling of Conducting-Bridge Random-Access Memory (CBRAM),” in TED, pp.1352-1360, 2011. [16] C.H. Wang, Y.H. Tsai, K.C. Lin, M.F Chang, Y.C. King, C. J. Lin, S.S. Sheu, Y.S. Chen, H.Y. Lee, F.T. Chen, M.J. Tsai, “Three-Dimensional 4F2 ReRAM With Vertical BJT Driver by CMOS Logic Compatible Process,” in TED, pp.2466-2472, 2011. [17] M.C. Hsieh, Y.W. Chin, Y.C. Lin, Y.D. Chih, K.H. Tsai, M.J. Tsai, Y.C. King, and C.J Lin,” A new laterally conductive bridge random access memory by fully CMOS logic compatible process”, in Jpn. J. Appl. Phys., pp.1-5, 2014. [18] Z. Fang, H. Y. Yu, X. Li, N. Singh, G. Q. Lo, and D. L. Kwong, “HfOx /TiOx /HfOx /TiOx Multilayer-Based Forming-Free RRAM Devices With Excellent Uniformity”, in EDL, VOL.32, NO.4, pp.566-568, 2011. [19] C.I. Hsieh, J.H. Jao, W.C. Chen, C.R. Wu, N.T. Shih, “Forming-free Resistive Switching of TiOx Layers with Oxygen Injection Treatments”, in VLSI-TSA, pp.1-2, 2011. [20] B. Gao, J. F. Kang, Y. S. Chen, F. F. Zhang, B. Chen, P. Huang, L. F. Liu, X. Y. Liu,Y. Y. Wang, X. A. Tran, Z. R. Wang, H. Y. Yu, Albert Chin, “Oxide-based RRAM: Unified microscopic principle for both unipolar and bipolar switching”, in IEDM, pp.17.4.1-17.4.4, 2011. [21] U. Russo, D. Ielmini, C. Cagli, A. L. Lacaita, “Self-Accelerated Thermal Dissolution Model for Reset Programming in Unipolar Resistive-Switching Memory (RRAM) Devices”, in TED, VOL.56, NO.2, pp. 193-200, 2009. [22] B. Gao, B. Sun, H. Zhang, L. Liu, X. Liu, R. Han, J. Kang, B. Yu, “Unified Physical Model of Bipolar Oxide-Based Resistive Switching Memory”, in EDL, VOL.30, NO.12, pp.1326-1328, 2009. [23] J. Kang, B. Gao, B. Chen, P. Huang, F. Zhang, L. Liu, X. Liu, “Physical Mechanism of Resistive Switching and Optimization Design of Cell in Oxide-based RRAM,” in ICSICT, pp.1-4, 2012. [24] B. Chen, Y. Lu, B. Gao, Y.H. Fu, F.F. Zhang, P. Huang, Y.S. Chen, L.F. Liu, X.Y. Liu, J.F. Kang, Y.Y. Wang, Z. Fang, H.Y. Yu, X. Li, X.P. Wang, N. Singh, G. Q. Lo, D. L. Kwong, “Physical Mechanisms of Endurance Degradation in TMO-RRAM”, in IEDM, pp.12.3.1-12.3.4, 2011. [25] M.J. Lee, Y. Park, B.S. Kang, S.E. Ahn, C. Lee, K. Kim, W. Xianyu, G. Stefanovich, J.H. Lee, S.J. Chung, Y.H. Kim, C.S. Lee, J. B. Park , I.G. Baek, I.K. Yoo, “2-stack ID-IR Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications”, in IEDM, pp.771-774, 2007. [26] Y.H. Tseng, C.E. Huang, C. H. Kuo, Y. D. Chih, C. J. Lin, “High Density and Ultra Small Cell Size of Contact ReRAM (CR-RAM) in 90nm CMOS Logic Technology and Circuits”, in IEDM , pp.1-4, 2009. [27] E. Linn, R. Rosezin, C. Kügeler and RainerWaser, “Complementary resistive switches for passive nanocrossbar memories,” in Nat. Mater., vol.9, no.5, pp.403-406, 2010. [28] X.A. Tran, B. Gao, J.F. Kang, X. Wu, L. Wu, Z. Fang, Z.R. Wang, K.L. Pey, Y.C. Yeo, A.Y. Du, M. Liu, B.Y. Nguyen, M.F. Li, H.Y. Yu, “Self-Rectifying and Forming-Free Unipolar HfOx based-High Performance RRAM Built by Fab-Avaialbe Materials”, in IEDM, pp.31.2.1-31.2.4, 2011. [29] Y. Sasago, M. Kinoshita, T. Morikawa, K. Kurotsuchi, S. Hanzawa, T. Mine, A. Shima, Y. Fujisaki, H. Kume, H. Moriya, N. Takaura and K. Torii, “Cross-point phase change memory with 4F2 cell size driven by low-contact-resistivity poly-Si diode”, in VLSI, pp.24-25, 2009. [30] I. G. Baek, D. C. Kim, M. J. Lee, H.-J. Kim, E. K. Yim, M. S. Lee, J. E. Lee, S. E. Ahn, S. Seo, J. H. Lee, J. C. Park, Y. K. Cha, S. O. Park, H. S. Kim, I. K. Yoo, U-In Chung, J. T. Moon and B. I. Ryu, “Multi-layer Cross-point Binary Oxide Resistive Memory (OxRRAM) for Post-NAND Storage Application”, in IEDM, pp.750-753, 2005. [31] G.Tallarida, N.Huby, B. Kutrzeba-Kotowska, S.Spiga, M.Arcari, G.Csaba, P.Lugli, “Low temperature rectifying junctions for crossbar non-volatile memory devices”, in IMW, pp.1-3, 2009. [32] J.J. Huang, Y.M. Tseng, W.C. Luo, C.W. Hsu, and T.H. Hou, “One Selector-One Resistor (1S1R) Crossbar Array for High-density Flexible Memory Applications”, in IEDM, pp.733-736, 2011. [33] A. Kawahara, R. Azuma, Y. Ikeda, K. Kawai, Y. Katoh, K. Tanabe, T. Nakamura, Y. Sumimoto, N. Yamada, N. Nakai, S. Sakamoto, Y. Hayakawa, K. Tsuji, S. Yoneda, A. Himeno, K. Origasa, K. Shimakawa, T. Takagi, T. Mikawa, K. Aono, “An 8Mb Multi-Layered Cross-Point ReRAM Macro with 443MB/s Write Throughput”, in ISSCC, pp.432-434, 2012. [34] T. Ghani, Armstrong M., Auth C.; Bost M., Charvat P., Glass G., Hoffmann T., Johnson K., Kenyon C., Klaus J., McIntyre B., Mistry K., Murthy A., Sandford J., Silberstein M., Sivakumar, S., Smith P., Zawadzki K., Thompson S., Bohr M., “A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors”, in IEDM, Dec.2003.
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