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作者(中文):陳書恩
作者(外文):Chen, Shu En
論文名稱(中文):應用於鰭式場效電晶體邏輯製程的高密度新型長形接觸點之電阻式隨機選取記憶體
論文名稱(外文):An Ultra High Density Slot Contact RRAM in Advanced FinFET CMOS Technology
指導教授(中文):林崇榮
指導教授(外文):Lin, Chrong Jung
口試委員(中文):蔡銘進
金雅琴
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學號:102063527
出版年(民國):104
畢業學年度:103
語文別:中文
論文頁數:59
中文關鍵詞:鰭式電晶體電阻式記憶體接觸點
外文關鍵詞:FinFETSlot Contact RRAMRRAMSCRRAM
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近年來,消費性電子產品如智慧型手機、穿戴式裝置、平板電腦等的普及以及消費者對於裝置多功能的需求,記憶體容量的提升以及更快的存取速度勢必會隨著科技的發展而被要求。記憶體可簡單的被歸類為揮發性(Volatile)以及非揮發性(Non-volatile),揮發性記憶體有著極快的寫入以及讀取速度優勢,然而面積大以及物理限制使得此種記憶體很難隨著製程發展微縮,非揮發性記憶體中快閃記憶體(Flash memory)主宰非揮發性記憶體市場,但是即將面臨的極限、高操作電壓以及微縮困難,使得新型記憶體得以加速發展,其中電阻式記憶體有著極高的潛力成為下一世代記憶體主流。
嵌入式電阻記憶體(Embedded RRAM)中代表性結構如點接觸式記憶體(Contact Resistive Random Access Memory, CRRAM)有著極佳的相容性,能夠相容於28奈米之前所有製程,然而隨著製程發展從2D結構進入3D鰭式電晶體,CRRAM勢必需要改良才有辦法在先進製程中實現。
本論文首次提出一種新型的鰭式場效電晶體長形接觸點電阻式隨機存取記憶體(Slot Contact Resistive Random Access Memory, SCRRAM),相容於先進鰭式場效電晶體邏輯製程,此種新電阻式記憶體不需要增加額外光罩或特殊製程步驟,並且單位元件面積只有0.051μm2,此種電阻式記憶體有著低操作電壓、低功耗、阻態轉換速度快之優點,而電性分析也顯示在直流/交流分析、可靠度、連續讀取測試以及150oC高溫烘烤測試表現出優秀的特性,NOR型陣列結構之可行性使得此種記憶體有很高的機會成為下一世代記憶體發展之主流。
CMOS logic compatible RRAMs have been proposed to meet the requirements of small cell size, fast programming speed, low power consumption, reliable data retention, and good endurance characteristics. However, all of these previous works are all based on a planar CMOS logic process and there is no good solution for FinFET CMOS process until now. By the need of high performance transistors in SOC, HKMG FinFET structure, process and transistor have been widely implemented in advanced CMOS fabrication in the years to come. Based on the new FinFET technology, in this study, a novel slot contact RRAM is proposed and fabricated by the pure 16nm FinFET CMOS logic process without additional process step or mask. The existing Ti-based Transition Metal Oxide (TMO) in FinFET slot contact module is exploited to be a reliable resistive storage node of the new RRAM cell, the n-type epi. SiP and the tungsten metal contact slot are served as bottom and top electrodes, respectively. By using the self-forming Ti-based TMO in FinFET slot contact process, the new SCRRAM is not only fully compatible with FinFET CMOS logic process but it also can operate at a low set voltage of 2.5V and a reset current of 60μA per cell. Moreover, the new FinFET SCRRAM also has excellent RRAM characteristics and superior reliability with an ultra small cell size of 0.051μm2, the results lead the new RRAM technology to become a very promising high density embedded NVM solution in the coming FinFET CMOS era.
摘要………………………………………………………..………..….i
Abstract………………………………………………………………. ii
致謝……………………………………………………………………iii
附圖目錄……………………………………………………………... vi
附表目錄…………………………………………………………….viii
第一章 序論…………………………………………………………...1
1.1 前言…………………………………………………………1
1.2 論文大綱……………………………………………………2
第二章 電阻式記憶體文獻回顧……………………………………...3
2.1 電阻式記憶體介紹…………………………………………3
2.1.1電阻式記憶體技術回顧…………...............................3
2.1.2初始化………………………………………...............5
2.1.3操作特性……………………………….……………4
2.1.4電阻式記憶體模型…………………………………...4
2.2 電阻式記憶體陣列………………………………………… 7
2.2.連通管原理及金氧半電晶體驅動陣列..........................7
2.2.2互補式電阻式記憶體陣列…………………………...7
2.2.3二極體驅動電阻式記憶體陣列……………………...8
2.3 小結………………………………………………………….9
第三章 長形接觸點電阻式記憶體(SCRRAM)………………….…22
3.1 鰭式電晶體結構簡介…………………………………..…22
3.2 SCRRAM之形成………………………………………....23
3.2.1矽鰭邊緣內縮……………………………………….23
3.2.2長形接觸點蝕刻窗錯位…………………………….24
3.3 陣列結構實現以及操作機制.............................................24
3.4 小結……………………………………………………….25
第四章 SCRRAM電性量測與分析………………………………...33
4.1 量測環境介紹…………………………………………….33
4.2 元件特性與操作最佳化………………………………….33
4.2.1直流分析與讀取最佳化………………………….....33
4.2.2交流脈衝分析……………………………………….34
4.3 可靠度量測與分析……………………………………….35
4.3.1資料儲存性分析………………………………...…..35
4.3.2讀取干擾測試……………………………………….36
4.3.3設置/重置干擾分析………………………………...36
4.4 小結……………………………………………………….37
第五章 總結………………………………………………………….53
參考文獻……………………………………………………………...54
[1] R.A. Bheda, J.A. Poovey, J.G. Beu, and T.M. Conte, “Energy Efficient Phase Change Memory Based Main Memory for Future High Performance Systems” , in IGCC, Washington, pp.1-8, 2011.
[2] R. E. Simpson, P. Fons, A. V. Kolobov, T. Fukaya, M. Krbal, T. Yagi and J. Tominaga, “Interfacial phase-change memory”, in Nature nanotechnology, pp.501-505, Jul 2011.
[3] J.C. Slonczewski, “Current-driven excitation of magnetic multilayers”, in Journal of Magnetism and Magnetic Materials, vol.159, pp.L1-L7, Jun. 1996.
[4] C.J. Lin, S.H. Kang, Y.J. Wang, K. Lee, X. Zhu, W.C. Chen, X. Li, W.N. Hsu,Y.C. Kao, M.T. Liu, W.C. Chen, Y.Lin, M. Nowak, N. Yu and L. Tran, ” 45nm Low Power CMOS Logic Compatible Embedded STT MRAM Utilizing a Reverse-Connection 1T/1MTJ Cell”, in IEDM, Baltimore, pp.1-4, Dec. 2009.
[5] C.Y. Lin, D.-Y. Lee, C.C. Lina, and T.Y. Tseng ,“Effect of thermal treatment on resistive switching characteristics in Pt/Ti/Al2O3/Pt devices”,in Surface Coatings Technol.,vol. 203, pp. 628–631, Dec .2008.
[6] I.S. Park, K.R. Kim, S. Lee and J. Ahn,”Resistance switching characteristics fornonvolatile memory operation of binarymetal oxides”, in Jpn. J. Appl. Phys., vol. 46,pp. 2172–2174, Apr. 2007.
[7] D. S. Jeong , z. Schroeder, and R. Waser,”Coexistence of bipolar and unipolar resistiveswitching behaviors in a Pt/TiO2/Ptstack”, in Electrochem Solid-State Lett., vol. 10,pp. G51–G53, 2007
[8] K.P. Chang,W.C. Chien,Y.C. Chen,E.K. Lai, S.C.g Tsai,S.H. Hsieh,Y.D.Yao,J. Gong;K.Y. Hsieh,R. Liu and C.Y. Lu, “Low-voltage and fast-speed forming processof tungsten oxide resistive memory,” in Extended Abstracts Int. Conf. Solid State Devices Mater., Tsukuba ,pp. 1168–1169, Sep .2008.
[9] Y.W. Chin, S.E.Chen, M.C. Hsieh, T.S. Chang, C.J. Lin, Y.C. King, “Point twin-bit RRAM in 3D interweaved cross-point array by Cu BEOL process”, in IEDM, Dec. 2014.
[10] M.C Hsieh, Y.C. Liao, Y.W. Chin, C.H. Lien, T.S. Chang, Y.D. Chih, Natarajan S, M.J.Tsai, Y.C. King, C.J. Lin, “Ultra high density 3D via RRAM in pure 28nm CMOS process”, in IEDM, Dec. 2013.
[11] W.C. Shen, C.Y. Mei, Y.D. Chih, S.S. Sheu, M.J. Tsai, Y.C. King, C.J. Lin, “High-K metal gate contact RRAM (CRRAM) in pure 28nm CMOS logic process”, in IEDM, Dec. 2012
[12] Y. Watanabe, J. G. Bednorz, A. Bietsch, Ch. Gerber, D. Widmer, A. Beck, and S. J. Wind, “Current-driven insulator-conductor transition and nonvolatile memory in chromium-doped SrTiO3 single crystals”, in Appl. Phys. Lett., vol.78, pp.3738–3740, 2001.
[13] A.Beck, J.G. Bednorz, C. Gerber, C. Rossel, D. Widmer, ”Reproducible swiching effect in thin oxide films for memory applications”, in Appl. Phys. Lett., 2000.
[14] C. Cagli, D. Ielmini, F. Nardi and A. L. Lacaita, “Evidence for threshold switching in the set process of NiO-based RRAM and physical modeling for set, reset, retention and disturb prediction”, in IEDM, pp.1-4, 2008.
[15] S. Yu, H.-S. Philip Wong, “Compact Modeling of Conducting-Bridge Random-Access Memory (CBRAM),” in TED, pp.1352-1360, 2011.
[16] C.H. Wang, Y.H. Tsai, K.C. Lin, M.F Chang, Y.C. King, C. J. Lin, S.S. Sheu, Y.S. Chen, H.Y. Lee, F.T. Chen, M.J. Tsai, “Three-Dimensional 4F2 ReRAM With Vertical BJT Driver by CMOS Logic Compatible Process,” in TED, pp.2466-2472, 2011.
[17] M.C. Hsieh, Y.W. Chin, Y.C. Lin, Y.D. Chih, K.H. Tsai, M.J. Tsai, Y.C. King, and C.J Lin,” A new laterally conductive bridge random access memory by fully CMOS logic compatible process”, in Jpn. J. Appl. Phys., pp.1-5, 2014.
[18] Z. Fang, H. Y. Yu, X. Li, N. Singh, G. Q. Lo, and D. L. Kwong, “HfOx /TiOx /HfOx /TiOx Multilayer-Based Forming-Free RRAM Devices With Excellent Uniformity”, in EDL, VOL.32, NO.4, pp.566-568, 2011.
[19] C.I. Hsieh, J.H. Jao, W.C. Chen, C.R. Wu, N.T. Shih, “Forming-free Resistive Switching of TiOx Layers with Oxygen Injection Treatments”, in VLSI-TSA, pp.1-2, 2011.
[20] B. Gao, J. F. Kang, Y. S. Chen, F. F. Zhang, B. Chen, P. Huang, L. F. Liu, X. Y. Liu,Y. Y. Wang, X. A. Tran, Z. R. Wang, H. Y. Yu, Albert Chin, “Oxide-based RRAM: Unified microscopic principle for both unipolar and bipolar switching”, in IEDM, pp.17.4.1-17.4.4, 2011.
[21] U. Russo, D. Ielmini, C. Cagli, A. L. Lacaita, “Self-Accelerated Thermal Dissolution Model for Reset Programming in Unipolar Resistive-Switching Memory (RRAM) Devices”, in TED, VOL.56, NO.2, pp. 193-200, 2009.
[22] B. Gao, B. Sun, H. Zhang, L. Liu, X. Liu, R. Han, J. Kang, B. Yu, “Unified Physical Model of Bipolar Oxide-Based Resistive Switching Memory”, in EDL, VOL.30, NO.12, pp.1326-1328, 2009.
[23] J. Kang, B. Gao, B. Chen, P. Huang, F. Zhang, L. Liu, X. Liu, “Physical Mechanism of Resistive Switching and Optimization Design of Cell in Oxide-based RRAM,” in ICSICT, pp.1-4, 2012.
[24] B. Chen, Y. Lu, B. Gao, Y.H. Fu, F.F. Zhang, P. Huang, Y.S. Chen, L.F. Liu, X.Y. Liu, J.F. Kang, Y.Y. Wang, Z. Fang, H.Y. Yu, X. Li, X.P. Wang, N. Singh, G. Q. Lo, D. L. Kwong, “Physical Mechanisms of Endurance Degradation in TMO-RRAM”, in IEDM, pp.12.3.1-12.3.4, 2011.
[25] M.J. Lee, Y. Park, B.S. Kang, S.E. Ahn, C. Lee, K. Kim, W. Xianyu, G. Stefanovich, J.H. Lee, S.J. Chung, Y.H. Kim, C.S. Lee, J. B. Park , I.G. Baek, I.K. Yoo, “2-stack ID-IR Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications”, in IEDM, pp.771-774, 2007.
[26] Y.H. Tseng, C.E. Huang, C. H. Kuo, Y. D. Chih, C. J. Lin, “High Density and Ultra Small Cell Size of Contact ReRAM (CR-RAM) in 90nm CMOS Logic Technology and Circuits”, in IEDM , pp.1-4, 2009.
[27] E. Linn, R. Rosezin, C. Kügeler and RainerWaser, “Complementary resistive switches for passive nanocrossbar memories,” in Nat. Mater., vol.9, no.5, pp.403-406, 2010.
[28] X.A. Tran, B. Gao, J.F. Kang, X. Wu, L. Wu, Z. Fang, Z.R. Wang, K.L. Pey, Y.C. Yeo, A.Y. Du, M. Liu, B.Y. Nguyen, M.F. Li, H.Y. Yu, “Self-Rectifying and Forming-Free Unipolar HfOx based-High Performance RRAM Built by Fab-Avaialbe Materials”, in IEDM, pp.31.2.1-31.2.4, 2011.
[29] Y. Sasago, M. Kinoshita, T. Morikawa, K. Kurotsuchi, S. Hanzawa, T. Mine, A. Shima, Y. Fujisaki, H. Kume, H. Moriya, N. Takaura and K. Torii, “Cross-point phase change memory with 4F2 cell size driven by low-contact-resistivity poly-Si diode”, in VLSI, pp.24-25, 2009.
[30] I. G. Baek, D. C. Kim, M. J. Lee, H.-J. Kim, E. K. Yim, M. S. Lee, J. E. Lee, S. E. Ahn, S. Seo, J. H. Lee, J. C. Park, Y. K. Cha, S. O. Park, H. S. Kim, I. K. Yoo, U-In Chung, J. T. Moon and B. I. Ryu, “Multi-layer Cross-point Binary Oxide Resistive Memory (OxRRAM) for Post-NAND Storage Application”, in IEDM, pp.750-753, 2005.
[31] G.Tallarida, N.Huby, B. Kutrzeba-Kotowska, S.Spiga, M.Arcari, G.Csaba, P.Lugli, “Low temperature rectifying junctions for crossbar non-volatile memory devices”, in IMW, pp.1-3, 2009.
[32] J.J. Huang, Y.M. Tseng, W.C. Luo, C.W. Hsu, and T.H. Hou, “One Selector-One Resistor (1S1R) Crossbar Array for High-density Flexible Memory Applications”, in IEDM, pp.733-736, 2011.
[33] A. Kawahara, R. Azuma, Y. Ikeda, K. Kawai, Y. Katoh, K. Tanabe, T. Nakamura, Y. Sumimoto, N. Yamada, N. Nakai, S. Sakamoto, Y. Hayakawa, K. Tsuji, S. Yoneda, A. Himeno, K. Origasa, K. Shimakawa, T. Takagi, T. Mikawa, K. Aono, “An 8Mb Multi-Layered Cross-Point ReRAM Macro with 443MB/s Write Throughput”, in ISSCC, pp.432-434, 2012.
[34] T. Ghani, Armstrong M., Auth C.; Bost M., Charvat P., Glass G., Hoffmann T., Johnson K., Kenyon C., Klaus J., McIntyre B., Mistry K., Murthy A., Sandford J., Silberstein M., Sivakumar, S., Smith P., Zawadzki K., Thompson S., Bohr M., “A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors”, in IEDM, Dec.2003.
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