近幾年來，由於分離閘快閃記憶體高寫入效率、低功率消耗和較不易發生過度抹除等好處，被廣泛使用於單機產品和內嵌式的應用。然而，其不對稱的元件結構限制了記憶體陣列的排列方式，像是AND型和NAND型等高密度的排列方式就完全不適用在傳統的內嵌式分離閘快閃記憶體上。本篇論文提出一種新型的分離閘快閃記憶體(AND-type Split Gate Flash)，此種記憶體可以使單一元件具有兩個位元的儲存能力，在0.18μm內嵌式快閃記憶體的技術中已被成功製造出來，以源極電子注入機制 （Source Side Injection, SSI）完成寫入，以福樂諾漢穿隧效應（FN Tunneling）達成抹除操作。電性分析顯示出其具備高寫入速度以及能夠經過多次寫抹操作，除此之外，優異的抗讀取干擾以及元件在150℃ 的環境下烘烤1000小時後，資料仍不會被翻轉，足以證明其優異的可靠度。
在陣列排列上此元件可以被排成AND型陣列，和傳統排列成NOR型的分離閘快閃記憶體相較之下可以減少50%的元件尺寸，本研究中，在0.18 μm內嵌式快閃記憶體的技術中成功實現了高密度的3Mb AND型Split Gate Flash陣列，此記憶體相容於原先的內嵌式快閃記憶體製程，具有高密度、足夠的讀取視窗和傑出的可靠度，可望在未來成為相當有競爭力的非揮發性快閃記憶體。

Nowadays, due to the benefits of its high program efficiency, low power consumption, and over-erase immunity, split gate flash cells are widely used in both stand-alone products and embedded applications. However, the asymmetric structure of spilt gate device limits the memory array arrangement. The high density array arrangements, such as AND and NAND, are not suitable for the conventional logic-based embedded spilt gate flash technology. In this thesis, we propose a novel AND split gate flash (ASG) to realize two-bits per cell operation in 0.18 μm embedded memory technology. By device and process optimization, this cell can operate at highly efficient source side injection (SSI) and FN-tunneling mechanism for program and erase, respectively. The electrical analysis shows fast program speed and good endurance. Besides, excellent disturb immunity and data retention at 150℃ for 1000 hours further prove its superior reliability.
This unique cell can be arranged in AND-type array, reducing 50% cell size compare to conventional spilt gate flash. In this study, a highly density 3Mb AND-type Split Gate Flash Memory array chip is successfully demonstrated in 0.18 embedded flash technology. This new cell featuring high density, large read window and outstanding reliability is one of the promising solution for flash applications.

摘要 I
Abstract II
致謝 III
內文目錄 IV
附圖目錄 VI
附表目錄 IX
第一章 序論 1
1.1非揮發性記憶體介紹 1
1.2論文內容大綱 3
第二章 分離閘快閃記憶體回顧與發展 4
2.1 Masuoka等人提出之快閃記憶體元件結構介紹 4
2.2 SIEPROM元件結構介紹 5
2.3 SISOS元件結構介紹 6
2.4 HIMOS元件結構介紹 7
2.5 SPIN元件結構介紹 7
2.6 Kianian等人提出之分離閘快閃記憶體結構介紹 8
第三章 分離閘快閃記憶體結構與操作原理 18
3.1 記憶體元件結構與製程 18
3.2 量測環境介紹 20
3.3 受測元件的操作機制 21
3.3.1 元件的寫入機制 21
3.3.2 元件的抹除機制 21
3.3.3 元件的讀取機制 22
第四章 分離閘快閃記憶體量測特性分析 35
4.1元件寫入操作分析 35
4.2 元件抹除操作分析 36
4.3元件讀取操作分析 36
4.4 元件可靠度分析 37
4.5 元件結構最佳化分析 38
4.6 小結 38
第五章 分離閘快閃記憶體之陣列 49
5.1 陣列結構的比較與最佳化 49
5.2 量測環境介紹 50
5.3 量測結果與操作分析 51
5.4 記憶體陣列寫入造成的讀取干擾分析 52
5.5 小結 53
第六章 結論 68
參考文獻 69

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