隨著科技的演進，連線延遲仍然主導著電路性能。當製程進入了32奈米的節點後，不同分層的佈局層有不同預設寬度的導線，這使得繞線延遲受到繞線的佈局層分配影響甚深。此外，當進入了次16奈米節點後，因為延遲受到導線的耦合影響越來越大以及不能任意得調整導線寬度來降低導線電容，這使得時序優化的問題很難以解決。這篇論文試著解決一個在全域繞線階段時考慮耦合效應以及通孔延遲的延遲取向之佈局層配置問題。而這邊提出利用概率性方法而建的找查表來估計耦合電容模型。未了考慮可繞性，使用了協商為基礎的架構來取得延遲和擁擠以及通孔數量之平衡。最後，提出的演算法可以透過使用平行導線以及非預設規則的導線來降低延遲。而實驗數據顯示了我們的佈局層配置演算法有很好的效益。

As technology advances, the interconnect delay gradually dominates the circuit performance but the emerging issues makes timing optimization become more complicated. Since 32nm nodes, different tiers of layers have different default wire widths such that the layer assignment of routing wires greatly impacts interconnect delay. Moreover, below 16nm nodes, because the wire coupling impacts delay more significantly and wire width cannot be arbitrarily sized to reduce wire capacitance, the timing optimization problem is harder to resolve. This thesis addresses a delay-driven layer assignment problem with consideration of via delay and coupling effect in the global routing stage. A look-up table method is proposed to estimate the coupling capacitance modeled by a probabilistic approach. In order to consider routability, a negotiation-based framework is presented to strike a good balance between delay, congestion, and via count. Finally, the proposed algorithm is able to use parallel wires and non-default-rule (NDR) wires to pursue better delay reduction instead of using wire sizing. The effectiveness of our layer assignment algorithm is well supported by extensive experimental results.

1 Introduction 1
2 Problem Formulation 4
2.1 Parallel Wires and NDR Wires 5
2.2 Wire Congestion Constraints 6
2.3 Delay Model 6
3 Parasitic Extraction 8
4 Delay-driven Layer Assignment 10
4.1 Algorithm flow 11
4.2 Single net layer assignments 14
4.2.1 Overview of DPLA 15
4.2.1 Find a minimum cost assignment 17
4.3 Delay Calculation 20
4.4 Node weighting 20
4.5 Threshold of using parallel wires and NDR wires 21
5 Experimental Results 26
5.1 Delay Impact from Coupling Capacitance 26
5.2 Threshold Setting of Parallel Wires and NDR Wires 27
5.3 Effectiveness of the Node Weighting 28
5.4 Effectiveness of Using Parallel and NDR Wires 29
6 Conclusions 31

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