隨著製程的演進，電晶體越做越小且越做越複雜，到16/14奈米以下鰭式電晶體（FinFET）技術的導入更是電子業界的一大進展，於設計再運用中，佈局遷移為ㄧ個重要的步驟。為了將28/20奈米以上的製程遷移成16奈米以下，device必須使用鰭式電晶體，所以設計規則改變了很多。鰭式電晶體的製程多了一條以前沒有的DRC 規則，就是所有的閘極都必須擺放在某個格線上，目前沒有工具能自動去遷移至16奈米以下，所以若要自動去遷移成16奈米以下，有一件事就是把所有的閘極都對齊到格線上。本篇論文提出ㄧ個方法自動將佈局中的閘極間距離保持在格子大小的倍數，最後只要其中ㄧ個閘極在格線上，則所有的閘極一定保證在格線上。

With the process development, transistors become smaller and more complicated.In 16/14 nm process, FinFETs make a huge progress in electronics industry. Layout migration is an important task in design reuse. In order to migrate the process from 28/20 nm to sub-16 nm, we need to use FinFETs, which make DRC rules change a lot. One of the DRC rules added in FinFETs is that all gates must be positioned on the grid lines. So far, there are no tools reported for migration to the sub-16 nm process automatically. If we want to achieve this goal, one issue we need to tackle will be how to eciently align gates to grid lines. Therefore, we propose in this thesis an approach to address this issue so as to facilitate the migration of a layout to the FinFET technology.

1 Introduction 1
1.1 Introduction . . . . . . . . . . . . . . . . . . . 1
2 Preliminaries and Problem Formulation 5
2.1 Preliminaries . . . . . . . . . . . . . . . . . . 5
2.2 Problem Formulation . . . . . . . . . . . . . . . .7
3 Algorithm 8
3.1 Algorithm Overview . . . . . . . . . . . . . . . . 8
3.2 Polygon Information Recording Stage . . . . . . . .9
3.3 Instance Movement Stage . . . . . . . . . . . . . 12
3.4 Connecting Stage . . . . . . . . . . . . . . . . .17
4 Experiment Results 24
5 Conclusion 35
References 37

[1] K. Lin, S. Kale, and A. Nigam,\Methodology for Automated Layout Migration for 90nm Itanium Processor Design," Proc Int. Symp. on Quality Electronic Design, pp.31-35, Mar.2004.
[2] X. Tang and X. Yuan,\Technology Migration Techniques for Simplied Layouts with Restric-tive Design Rules," Proc. Int. Conf. on Computer Aided Design,pp. 655{660, Nov. 2006.
[3] Y. Choi, I. Chun, B. Kim, and H. Shin, \A Technology Migration Method Using Rectangle-based Layout onversion," Proc. Int. Conf. Asia-Pacic ASIC, pp. 274{277 Aug. 2004.
[4] S. H. Batterywala, S. Bhattacharya, S. Rajagopalan, H.-K. T.Ma and N.V. Shenoy, \CellSwapping Based Migration Methodology for Analog and Custom Layouts," Proc. Int. Symp.Quality Electronic Design, pp. 450{455, March 2008.
[5] H. Said and H. M. Abbas, \A Novel General Graph-Based Simplex Algorithm Applied to IC Layout Compaction and Migration," Proc . Int. Design and Test Workshop, pp. 241 - 246, Nov. 2007.
[6] J. Lakos, "Technology Retargeting for IC Layout," Proc. Design Automation Conf., pp.460{465, Jun. 1997.
[7] Pcell : https://en.wikipedia.org/wiki/PCell
[8] C. Kingsley, \A Hierarchical, Error-tolerant Compactor," Proc. Design Automation Conf.,pp. 126{132, Jun. 1984.
[9] D. Marple, \A Hierarchy Preserving Hierarchical Compactor," Proc. Design Automation Conf., pp. 375{381, Jun. 1990.
[10] J-F. Lee and D. Tang, \Himalayas - A Hierarchical Compaction System with a Minimized Constraint Set," Proc. Int. Conf.on Computer Aided Design, pp.150{157, Nov.1992.
[11] R. O. Topaloglu, \Design with FinFETs: Design Rules, Patterns, and Variability," Proc. Design Automation Conf., pp. 569 - 571, Nov. 2013.
[12] GDSII : https://en.wikipedia.org/wiki/GDSII
[13] GDSII : http://www.artwork.com/gdsii/gdsii/index.htm
[14] Kbool boolean library : https://github.com/Heeks/libarea/tree/master/kbool
[15] T. - C. Lin, Implicit Connection Graph-based Maze Routing for Layout Migration, Master
Thesis National Tsing Hua University, Taiwan, July 2015.
[16] Calibre nmLVS: http://www.mentor.com/products/ic nanometer design/verication-signo/physical-verication/