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作者(中文):張瑞麟
作者(外文):Chang, Jui Lin
論文名稱(中文):考慮密度平整限制之虛擬金屬填充
論文名稱(外文):Dummy Fill Insertion Considering Density Uniformity Constraint
指導教授(中文):麥偉基
指導教授(外文):Mak, Wai Kei
口試委員(中文):李毅郎
王廷基
口試委員(外文):Li, Yih Lang
Wang, Ting Chi
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學號:102062623
出版年(民國):104
畢業學年度:103
語文別:英文
論文頁數:29
中文關鍵詞:虛擬金屬填充線性規劃化學機械研磨可製造性設計
外文關鍵詞:Dummy fill insertionLinear ProgrammingChemical Mechanical PolisingDesign for Manufacturability
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隨著現今超大型積體電路(VLSI)製程尺寸越來越小,也越來越複雜。一個晶片當中所需要的層數也會越來越多,這伴隨而來的問題就是會使得我們晶圓表面凹凸不平的情況會加劇,為了可以配合現今光蝕刻的技術,我們需要一個表面平坦的晶圓。否則可能會導致我們做光蝕刻時造成錯誤。而化學機械平坦化(CMP)是現在製程技術當中最能夠確保晶圓表面平整也最廣泛被使用的一項技術。但為了使CMP可以完美的運作,我們必須確保晶圓表面密度分布的平均,CMP結果的好壞與晶圓表面密度分布平均與否有很大的關聯,所以我們透過使用虛擬金屬填充的方法來使得我們晶圓表面密度分布平均,進而提升IC製程時的良率。我們使用Liner Programming(LP)的方法來得到每個子區塊理想的密度,再透過我們有效率的虛擬金屬填充方法填入虛擬金屬。我們與ICCAD 2014比賽的前三名隊伍有著相當的實驗結果。
As the shrinking of device geometries scale, there is an inevitable need for better planarization of the multilevel interconnect structures. To meet today's advanced lithography methods, we need a planar surface. Or may leads to bad lithography results. CHEMICAL MECHANICAL POLISHING(CMP) is the planarizing technique of
options to generate a good planarity result. But there is one problem for CMP to work perfectly, it can not have large stretches of metal or non-metal regions. Dummy fill has been demonstrated to be an effective technique to fix the planarity issue and to improve the manufacturability for advanced integrated circuit (IC) designs. We propose an liner programming (LP) formulation with some new considerations involved to determine the density of each region and an efficient fill insertion flow. Comparing with the experimental achievement for ICCAD 2014 contest benchmarks, we have a comparable result.
Acknowledgement i
Abstract ii
1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . 1
1.2 Previous Works . . . . . . . . . . . . . . 2
1.3 Organization . . . . . . . . . . . . . . . 6
2 Preliminaries 7
2.1 DRC and Objectives . . . . . . . . . . . . 7
2.1.1 Design Rules . . . . . . . . . . . . . . 7
2.1.2 Minimize Performance Degradation . . . . 8
2.1.3 Minimize Variation . . . . . . . . . . . 8
2.1.4 Minimize Line Hotspot . . . . . . . . . 8
2.1.5 Minimize Outliers Hotspot . . . . . . . 9
2.2 Problem Formulation . . . . . . . . . . . 9
2.3 R*-tree . . . . . . . . . . . . . . . . . 9
3 Method 11
3.1 LP Formulation . . . . . . . . . . . . . 12
3.2 LP Parameters Generation . . . . . . . . 15
3.3 Fill Insertion . . . . . . . . . . . . . 17
4 Experiment 22
4.1 Experimental Environment . . . . . . . . 22
4.2 Results and Screenshots . . . . . . . . . 23
5 Conclusion 27
Reference 28
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