帳號:guest(3.15.29.119)          離開系統
字體大小: 字級放大   字級縮小   預設字形  

詳目顯示

以作者查詢圖書館館藏以作者查詢臺灣博碩士論文系統以作者查詢全國書目
作者(中文):林鼎鈞
作者(外文):Lin, Ting Chun
論文名稱(中文):為了製程遷徙的基於隱性連通圖的迷宮繞線
論文名稱(外文):Implicit Connection Graph Maze Routing for Layout Migration
指導教授(中文):麥偉基
指導教授(外文):Mak, Wai Kei
口試委員(中文):王廷基
李毅郎
口試委員(外文):Wang, Ting Chi
Li, Yih Lang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學號:102062622
出版年(民國):104
畢業學年度:103
語文別:英文
論文頁數:28
中文關鍵詞:製程遷徙隱性連通圖迷宮繞線
外文關鍵詞:layout MigrationImplicit Connection GraphMaze Routing
相關次數:
  • 推薦推薦:1
  • 點閱點閱:142
  • 評分評分:*****
  • 下載下載:6
  • 收藏收藏:0
隨著超大型積體電路(VLSI )製程越來越小,要設計一個電路變
得越來越困難且耗時。製程遷徙是指當我們希望可以將電路從當
前的製程轉換到一個比較新穎的製程以提升效能時所做的動作,
而在許多類比電路中設計一個電路並非非常容易的, 因此如果有
一個的製程遷徙工具可以有效率的自動將電路做製程遷徙會是十
分有貢獻的。在將整個電路做縮小時, 可能會有些區塊無法縮小
至目標大小, 導致整個電路中不同區塊的縮放比例不同, 此現象
會導致不同區塊間的連線斷線, 為了解決此一問題我們的方法會
自動的去偵測出在做縮小前與縮小後物件的相連關係, 當發現有
兩個物件在縮小前後的先連關係不同便是我們需要去做繞現的地
方。而做繞線的部分我們會分成兩部分, 第一部分是一個簡單的
迷宮繞線但會產生一些冗贅的轉彎, 因此我們會再做完第二部分
來解決這個問題。實驗結果顯示我們在真實的電路中, 這種問題
可以完全解決, 並且沒有違反製程規定。
With advanced Very-Large-Scale Integration (VLSI) technology, migration method is
more important in analog circuit or some special custom design. Sometimes two blocks in
circuit will be migrated with different scale factor, and result in some connection between
two blocks broken. To solve the problem described before, we propose a scanline base
break point detection method that can construct the connection between polygons efficient.
After compare the connection between non-sizing and sizing, we can obtain all break point
what we need to route. To route the break point, an implicit connection graph base maze
router is proposed, it can fully use the routing resource and get a small bend solution. As
the result, our router use in layout migration method has a DRC clean solution in a real
case.
ii
Acknowledgement i
Abstract ii
1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Preliminaries 5
2.1 R*-tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Implicit Connection Graph . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Algorithm 7
3.1 Break Point Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.1 Scanline Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.2 Break Polygon Set Detection . . . . . . . . . . . . . . . . . . . . . 13
3.1.3 Angle 45 Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Maze Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.1 Construct Routing Graph . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.2 Pass1:Normal Maze Route . . . . . . . . . . . . . . . . . . . . . . 16
iii
3.2.3 Pass2:Minimal Bend Routing . . . . . . . . . . . . . . . . . . . . 17
4 Experiment Result 19
5 Conclusion 26
Reference 27
[1] Ulrich Lauther, “An O(N logN) Algorithm For Boolean Mask Operations,” in Design
Automation Conference,” 15th, pp. 555–562, 1981.
[2] Kuang-Wei Chiang, Surendea Nahar and Chi-Yuan Lo, “Time-Efficient VLSI Artwork
Analysis Algorithms in GOALIE2,” in Transctions on Computer-Aided Design”
, pp.640–648, 1989.
[3] Miles Ohlrich, Carl Ebeling, Eka Ginting and Lisa Sather, “SubGemini: Identifying
SubCircuits using a Fast Subgraph Isomorphism Algorithm,” inDesign Automation
Conference,” 30th, pp.31–37, 1993.
[4] Carl Ebeling, “GeminiII A Decond Generation Layout Validation Program,” in IEEE”,
pp322–325, 1988.
[5] Thomas G. Szymanski, “Space Efficient Algorithms for VLSI Artwork Analysis,” in
Design Automation Conference,” 20th, pp. 734–739, 1983.
[6] Yih-Lang Li, Hsin-Yu Chen and Chih-Ta Lin, “NEMO: A New Implicit-Connection-
Graph-Based Gridless RouterWithMultilayer Planes and Pseudo Tile Propagation,” in
Transctions on Computer-Aided Design” ,pp705–718, April 2007.
[7] Hsin-Yu Chen, Yih-Lang Li and Zhi-Da Lin, “NEMO: A New Implicit Connection
Graph-Based Gridless Router with Multi-Layer Planes and Pseudo-Tile Propagation,”
in International Symposium on Physical Design”, pp64–71, April 2006.
[8] Le-Chin Eugene Liu, Hsiao-Ping Tseng and Carl Sechen, “Chip-Level Area Routing,”
in International Symposium on Physical Design,”, 1998.
[9] Jason Cong, Jie Fang and Kei-Yong Khoo, “An Implicit Connection GraphMaze Routing
Algorithm for ECO Routing,” in International Conference on Computer-Aided Design”,
1999.
[10] Yih-Lang Li,Member, IEEE, Jin-Yih Li, andWen-Bin Chen, “An Efficient Tile-Based
ECO Router Using Routing Graph Reduction and Enhanced Global Routing Flow,”
in TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS
AND SYSTEMS”, pp345–358, February 2007.
[11] Jason Cong, Jie Fang and Kei-Yong Khoo, “DUNEA multilayer gridless routing system,”
in Transactions on Computer Aided Design”, pp 633–647, 2001.
[12] Lee, “An algorithm for path connection and its application,” in IRE Trans. Electronic
Computer”, 1961.
[13] https : //en.wikipedia.org/wiki/R ∗ tree
[14] http : //www.virtualroadside.com/
[15] Antonin Guttman, “R-trees: a dynamic index structure for spatial searching,” in SIGMOD,”,
pp47–57, 1984.
 
 
 
 
第一頁 上一頁 下一頁 最後一頁 top
* *