|
[1] M.-C. Kim, J. Hu, and N. Viswanathan, “Iccad-2014 cad contest in incremental timingdriven placement and benchmark suite,” in Proceedings of the 32th Annual International Conference on Computer-Aided Design, ser. ICCAD ’14. Piscataway, NJ, USA: IEEE Press, 2014, pp. 361–366. [2] I. Markov, J. Hu, and M.-C. Kim, “Progress and challenges in vlsi placement research,” in Proceedings of the 30th Annual International Conference on Computer-Aided Design, ser. ICCAD ’12, Nov 2012, pp. 275–282. [3] K. Rajagopal, T. Shaked, Y. Parasuram, T. Cao, A. Chowdhary, and B. Halpin, “Timing driven force directed placement with physical net constraints,” ISPD ’03 Proceedings of the 2003 international symposium on Physical design, pp. 60–66, 2003. [4] Y.-C. Chou and Y.-L. Lin, “A performance-driven standard-cell placer based on a modified force-directed algorithm,” ISPD ’01 Proceedings of the 2001 international symposium on Physical design, pp. 24–29, 2001. [5] T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, “Ntuplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints,” in IEEE TCAD, vol. 27, pp. 1228–1240, July 2008. [6] M.-C. Kim, D.-J. Lee, and I. Markov, “Simpl: An effective placement algorithm,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions, vol. 31, pp. 50–60, January 2012. [7] W.-K. Chow, J. Kuang, X. He, W. Cai, and E. F. Young, “Cell density-driven detailed placement with displacement constraint,” ISPD ’14 Proceedings of the 2014 on International symposium on physical design, pp. 3–10, 2014. [8] C. Chu and Y.-C. Wong, “Flute: Fast lookup table based rectilinear steiner minimal tree algorithm for vlsi design,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, no. 1, pp. 70–83, Jan 2008. [9] N. Gala, J. J. Kavalam, V. Sudharshan, S. Balachandran, and N. Chandrachoodan, “Iitimer,” 2013. [10] D. Sinha, L. Guerra e Silva, J. Wang, S. Raghunathan, D. Netrabile, and A. Shebaita, “Tau 2013 variation aware timing analysis contest,” in Proceedings of the 2013 ACM International Symposium on International Symposium on Physical Design, ser. ISPD ’13. New York, NY, USA: ACM, 2013, pp. 171–178. [11] P. Saha, I. MCKV Inst. of Eng., Liluah, and T. Samanta, “Obstacle avoiding rectilinear clock tree construction with skew minimization,” VLSIVLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference, pp. 387–392, January 2014. [12] P. Saha, S. Saha, and T. Samanta, “Rectilinear steiner clock tree routing technique with buffer insertion in presence of obstacles,” VLSI Design (VLSID), 2015 28th International Conference, pp. 447–451, January 2015. [13] C. Lee, M. Potkonjak, and W. Wolf, “System-level synthesis of application specific systems using a* search and generalized force-directed heuristics,” in Proceedings of the 9th International Symposium on System Synthesis, ser. ISSS ’96. Washington, DC, USA: IEEE Computer Society, 1996, pp. 2–. [14] M. Dodo, F. Andriamanampisoa, P. Torguet, and J. P. Jessel, “A new method to optimize the force-directed placement for 3d large graph drawing,” in Proceedings of the 5th International Conference on Computer Graphics, Virtual Reality, Visualisation and Interaction in Africa, ser. AFRIGRAPH ’07. New York, NY, USA: ACM, 2007, pp. 145–149. [15] M. Burstein and M. N. Youssef, “Timing influenced layout design,” in Proceedings of the 22Nd ACM/IEEE Design Automation Conference, ser. DAC ’85. Piscataway, NJ, USA: IEEE Press, 1985, pp. 124–130. [16] T. T. Kong, “A novel net weighting algorithm for timing-driven placement,” ICCAD ’02 Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, pp. 172–176, 2002. [17] B. Riess and G. Ettelt, “Speed: fast and efficient timing driven placement,” Circuits and Systems, 1995. ISCAS ’95., 1995 IEEE International Symposium, vol. 1, pp. 377–380, 1995. [18] M. A. B. Jackson and E. S. Kuh, “Performance-driven placement of cell based ic’s,” DAC ’89 Proceedings of the 26th ACM/IEEE Design Automation Conference, pp. 370–375, 1989. [19] W. Swartz and C. Sechen, “Timing driven placement for large standard cell circuits,” Design Automation, 1995. DAC ’95. 32nd Conference, pp. 211–215, 1995. Bibliography 30 [20] A. Chowdhary, K. Rajagopal, S. Venkatesan, T. Cao, V. Tiourin, Y. Parasuram, and B. Halpin, “How accurately can we model timing in a placement engine?” DAC ’05 Proceedings of the 42nd annual Design Automation Conference, pp. 801–806, 2005. [21] M. Moffitt, D. Papa, Z. Li, and C. Alpert, “Path smoothing via discrete optimization,” Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, pp. 724–727, June 2008. [22] N. Viswanathan, G.-J. Nam, J. A. Roy, Z. Li, C. J. Alpert, S. Ramji, and C. Chu, “Itop: integrating timing optimization within placement,” ISPD ’10 Proceedings of the 19th international symposium on Physical design, pp. 83–90, 2010. |