技術演進(technology migration)在產品週期中扮演很重要的角色，比較被關注的項目為layout compaction 的重新使用和硬體程式語言的重新使用，但有關flip-chip的繞線卻乏人問津。錫球(bumps)的個數也隨著技術演進的腳步逐漸減少，因此在flip-chip上做RDL 繞線的問題越來越複雜。這篇論文是在解決在錫球(bumps)個數有限的情況下，如何在最短線長的目標下進行RDL 繞線，我們所採用的方法是minimum cost maximum flow 演算法，實驗結果顯示我們的方法可以比maze routing的方法線長減少約69%

Technology migration plays a critical role in the time-to-market competition. Most existing works focus on layout compaction or hardware description language re-synthesis, and pay little attention to the I/O interface in flip chips. The complication of bumping process as well as electrical and reliability considerations prevent the bumps from scaling with transistor sizes. On the other hand, the number of signal bumps cannot be reduced and sometimes even increases due to the demands for wider bandwidth and various peripheral devices. As a result, the allocated die area for I/O can no longer afford the number of bumps a chip requires. This issue, known as bump encroachment, puts a stringent requirement on the redistribution layer (RDL) routing. In this paper, we first formulate the problem of RDL routing with bump encroachment, and then propose a network flow based algorithm to efficiently address it. Experimental results on a few benchmarks with parameters extracted from industrial designs show that compared with a maze routing-based approach, our algorithm can achieve up to 69% wirelength reduction.

中文摘要 ii
Acknowledgement iii
Abstract iv
List of Figures vi
List of Tables vii
Chapter 1 Introduction 1
Chapter 2 Background and Motivation 4
2.1 Technology Migration 4
2.2 RDL Routing 4
Chapter 3 Problem Formulation 6
Chapter 4 Algorithm 7
4.1 Routing Model Construction 8
4.2 P/G Trunk Insertion 8
4.3 Connecting P/G Trunks and Signal Traces to Bumps by Network Flow 12
4.4 Post-Processing 13
Chapter 5 Experimental Result 14
Chapter 6 Conclusion 16
Chapter 7 Reference 18

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