在過去幾年裡處理器運算的主流為集結 CPU 和 GPU 的異質多核心架構,異質多核心架 構提供了良好的計算效能和靈活性。能同時使用 CPU 和 GPU 來做運算是表現異質多核心架 構良好效能的最基本方式,但是現在許多模擬異構架構的實驗都只研究 CPU host 端執行程式 呼叫 GPU 去做運算,這樣的方式並不能完整的顯示出異質多核心架構的優點和效能。因此我 們提出了一個混合 CPU 和 GPU 核心軌跡的方法來使 NOC 軌跡模擬器實現同時使用 CPU 和 GPU 做運算的異質多核心構架構。在這篇論文中我們的方法分成了三個部分:產生軌跡部分、 軌跡驅動器的模擬部分以及驗證有效性的部分。最後我們的實驗結果表示混合的軌跡可以得 到差不多的平均網路延遲時間,實驗結果也得到了 1.21%的平均誤差。

Over the last few years, heterogeneous architecture that integrates CPU and GPU together has become popular. It provides good computational performance, flexibility, and power efficiency. An ideal heterogeneous architecture should be able to execute CPU devices and GPU devices at the same time and allocate the computations freely between CPU and GPU. Unfortunately, existing simulators for heterogeneous architecture can only run either CPU host program with GPU kernels or CPU kernels, but not both. This hinders the research on heterogeneous architecture designs. To overcome this limitation, we propose in this thesis an interim solution that mixes CPU and GPU kernel traces to facilitate heterogeneous architecture research that uses trace-driven simulations, such as Network-on-Chip (NoC). To evaluate the feasibility of the proposed method, we compare the performance data reported by a NoC simulator, Garnet, using the mixed traces with those using a reference trace, both are taken from the heterogeneous architecture simulator, Multi2Sim. Our experimental results show that mixing traces can generate an average network latency very similar to the reference trace, with an average error of 1.21%.

1. Introduction 1
2. Related Works 4
3. Methodology 5
3.1. Mixing Trace Method 5
3.2. Reference Trace 8
3.3. Trace Generation Phase 10
3.4. Trace-Driven Simulation Phase 13
3.5. Verification Availability Phase 16
4. Experiments 18
4.1. Experimental Settings 18
4.2. Experimental Results 19
5. Conclusion 22

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