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作者(中文):王瀅捷
作者(外文):Wang, Ying-Chieh
論文名稱(中文):硬體線程級投機效能分析
論文名稱(外文):Hardware Thread-Level Speculation Performance Analysis
指導教授(中文):李哲榮
指導教授(外文):Lee, Che-Rung
口試委員(中文):周志遠
許慶賢
口試委員(外文):Jerry Chou
Hsu, Ching-Hsien
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學號:102062557
出版年(民國):104
畢業學年度:103
語文別:英文
論文頁數:47
中文關鍵詞:線程級投機效能分析
外文關鍵詞:Thread-Level SpeculationPerformance Analysis
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線程級投機是一種平行的架構。線程級投機可以免除直接編譯平行程式時所需的問題分析,且這對於程式開發者建立平行程式是很有幫助的。然而,對於平行程式來說,效能才是最重要的問題。因此,我們分析IBM Blue Gene/Q 電腦上硬體線程級投機的效能。
此篇論文會展示在IBM Blue Gene/Q 電腦上硬體線程級投機的效能模型。此模型有很好的效能預測,也經由實驗驗證過。這個模型能夠幫助我們了解利用特殊目的的線程級投機可以讓需要以單一執行來避免記憶體衝突的程式得到多少潛在的效能加速。基於分析和測量線程級投機的運作和成本,我們推出一個能夠幫助我們利用這個硬體的特色的策略。除此之外,我們比較了硬體線程級投機和OpenMP的效能。基於效能分析,我們給了一個方向,幫助我們決定硬體線程級投機和OpenMP哪個效能較好。這個結果不但可以幫助使用者利用程級投機,同時也能提供未來線程級投機架構設計改進的方向。
Thread-Level Speculation (TLS) is one of the parallel frameworks. TLS can avoid the analysis problem of compiler-directed code parallelization and this is helpful for programmers to generate parallel programs. However, the performance is the most important issue for parallel programs. Therefore, we analyse the performance of hardware Thread-Level Speculation (TLS) in the IBM Blue Gene/Q computer.

This paper presents a performance model for hardware Thread-Level Speculation (TLS) in the IBM Blue Gene/Q computer. The model shows good performance prediction, as verified by the experiments. The model helps to understand potential gains from using special purpose TLS hardware to accelerate the performance of codes that, in a strict sense, require serial processing to avoid memory conflicts. Based on analysis and measurements of the TLS behavior and its overhead, a strategy is proposed to help utilize this hardware feature. Furthermore, we compare the performance of hardware Thread-Level Speculation and OpenMP. Based on the performance analysis, we give a direction for deciding between this two parallel frameworks. And the results can not only help users to utilize the TLS but also suggest potential improvement for the future TLS architectural designs.
1 Introduction 3
2 Background 6
3 Timing Analysis on Thread-level Speculation 9
3.1 Performance model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.1 Execution without any conflict . . . . . . . . . . . . . . . . . . 10
3.1.2 Execution with single conflict . . . . . . . . . . . . . . . . . . 10
3.1.3 Execution with two conflicts . . . . . . . . . . . . . . . . . . . 14
3.1.4 Execution with more than 2 conflicts . . . . . . . . . . . . . . 16
3.2 Rollback estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 Comparison of Thread-Level Speculation and OpenMP 23
4.1 Timing analysis on OpenMP . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 Performance comparison . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 Experiments 29
5.1 Experiments of Thread-Level speculation performance model . . . . . 29
5.2 Experiments of OpenMP performance model . . . . . . . . . . . . . . 32
5.3 Experiments of comparison between OpenMP and Thread-Level Speculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.3.1 Experiments on sample hashing program . . . . . . . . . . . . 34
5.3.2 Experiments on LAMMPS . . . . . . . . . . . . . . . . . . . . 37
5.3.3 Experiments on GROMACS . . . . . . . . . . . . . . . . . . . 37
6 Discussion and conclusion 43
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