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作者(中文):林雪如
作者(外文):Lin, Hsueh Ju
論文名稱(中文):減輕扇出晶圓級封裝中晶片位移之方法
論文名稱(外文):A Methodology for Alleviating Die Shift of Fan-Out Wafer-Level Packaging (FOWLP)
指導教授(中文):張世杰
指導教授(外文):Chang, Shih Chieh
口試委員(中文):王廷基
黃錫瑜
口試委員(外文):Wang, Ting Chi
Huang, Shi Yu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學號:102062523
出版年(民國):104
畢業學年度:103
語文別:英文中文
論文頁數:30
中文關鍵詞:晶圓級封裝扇出晶圓級封裝晶片位移浸潤式顯影
外文關鍵詞:Wafer-Level Packaging (WLP)Fan-Out Wafer-Level Packaging (FOWLP)Die shiftImmersion lithography
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扇出晶圓級封裝(Fan-Out Wafer-Level Packaging, FOWLP)是一種當晶片仍在晶圓上時就進行封裝的封裝型態,亦是近年來備受矚目的先進封裝之一。然而,扇出晶圓級封裝在製程中會發生「晶片位移」的問題。晶片位移使得晶片離開原先的位置,造成其與繞線層無法正確連接,因而導致晶片錯誤。許多的研究都指出:晶片會以放射狀的趨勢從晶圓中心向外位移。本論文將此趨勢納入考量,提出了兩種創新的方法來減輕晶片位移所造成的問題。而實驗結果顯示了發生晶片位移的12吋與18吋扇出晶圓級封裝,在使用我們的方法後,晶片位移的問題得以降低,其良率也因此能大幅提升。
Fan-out Wafer Level Packaging (FOWLP), which performs the packaging of dies while still being part of the wafer, has attracted a lot of attention for advanced electronic products in recent years. However, in FOWLP, there is a mechanical problem, the die shift problem which can cause a die to be shifted away from its original position on the carrier for FOWLP. The die shift problem can lead to the misalignment of contacts and therefore cause failure of dies. It has been shown by several researches that the majority of dies are shifted away from the center. Taking into account this shifting trend, in this paper, we propose an alleviation methodology integrating two novel approaches to alleviate the die shift problem. The experiments show that the die shift of 12- and 18-inch FOWLP can be alleviated and the yield will be highly improved.
List of Contents
List of Contents VIII
List of Figures IX
List of Tables X
CHAPTER 1 INTRODUCTION 1
CHAPTER 2 DIE SHIFT ISSUE FOWLP 9
CHAPTER 3 ALLEVIATION METHODOLOGY 11
3.1 Two Approaches for the Die Shift Problem 11
3.1.1 Immersion Lithography (IL) with Different Liquids 11
3.1.2 Exposure Position Adjustment 13
3.2 Alleviation Algorithm 13
CHAPTER 4 EXPERIMENTS 22
CHAPTER 5 CONCLUSIONS 26
REFERENCES 27
[1] M. Topper, T. Baumgartner, M. Klein, T. Fritzsch, J. Roeder, M. Lutz, M. von Suchodoletz, and H. Oppermann, "Low Cost Wafer-Level 3-D Integration without TSV", Proc. Electronic Components and Technology Conference (ECTC), 2009, pp. 339-344.
[2] Y. Okayama, Y. Yanase, K. Saitou, H. Kobayashi, M. Nakasato, T. Yamamoto, and R. Usui, "Development of a novel Wafer-Level-Packaging Technology using Laminating Process", Proc. Electronic Components and Technology Conference (ECTC), 2009, pp. 892-897.
[3] X.J. Fan, B. Vaira, and Q. Han, "Design and Optimization of Thermo-mechanical Reliability in Wafer Level Packaging", Microelectronics Reliability, 2010, vol. 50 (4), pp. 536-546.
[4] B. Huang, H.D. Chang, S. Liu, M. Liao, L. Lee, S. Lin, and B. Hsu, "Novel Method of Wafer Level Packaging in the Field of MEMS", Proc. Assembly and Circuits Technology Conference (IMPACT), 2012, pp. 303-306.
[5] X. Fan, "Wafer Level Packaging (WLP): Fan-in, Fan-out and Three-dimensional Integration", Proc. Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE), 2010, pp. 1-7.
[6] T. Hasegawa, H. Abe, and T. Ikeuchi, "Wafer Level Compression Molding Compounds", Proc. Electronic Components and Technology Conference (ECTC), 2012, pp. 1400-1405.
[7] C.H. Khong, A. Kumar, X. Zhang, G. Sharma, S.R. Vempati, K. Vaidyanathan, J.H.-S Lau, and D.-L. Kwong, "A Novel Method to Predict Die Shift During Compression Molding in Embedded Wafer Level Package", Proc. Electronic Components and Technology Conference (ECTC), 2009, pp. 535-541.
[8] H.S. Ling, B. Lin, C.S. Choong, S.D. Velez, C.T. Chong, and X. Zhang, "Comprehensive Study on the Interactions of Multiple Die Shift Mechanisms During Wafer Level Molding of Multichip-Embedded Wafer Level Packages", Components, Packaging and Manufacturing Technology (CPMT), 2014, vol. 4 (6), pp. 1090-1098.
[9] L. Ji, D.V. Sorono, T.C. Chai, and X. Zhang, "3-D Numerical and Experimental Investigations on Compression Molding in Multichip Embedded Wafer Level Packaging", Components, Packaging and Manufacturing Technology (CPMT), 2013, vol. 3 (4), pp. 678-687.
[10] L. Ji, H.J. Kim, F.X. Che, S. Gao, and D, Pinjala, "Numerical Study of Preventing Flow-induced Die-shift in the Compression Molding for Embedded Wafer Level Packaging", Proc. Electronics Packaging Technology Conference (EPTC), 2011, pp. 406-411.
[11] L. Bu, S. Ho, S.D. Velez, T. Chai, and X. Zhang, "Investigation on Die Shift Issues in the 12-in Wafer-Level Compression Molding Process", Components, Packaging and Manufacturing Technology (CMPT), 2013, vol. 3 (10), pp. 1647-1653.
[12] T. Braun, K.-F. Becker, S. Voges, T. Thomas, R. Kahle, J. Bauer, R. Aschenbrenner, and K.-D. Lang, "From Wafer Level to Panel Level Mold Embedding", Proc. Electronic Components and Technology Conference (ECTC), 2013, pp. 1235-1242.
[13] A. Kumar, X. Dingwei, V.N. Sekhar, S. Lim, C. Keng, G. Sharma, V.S. Rao, V. Kripesh, J.H. Lau, and D.-L. Kwong, "Wafer Level Embedding Technology for 3D Wafer Level Embedded Package", Proc. Electronic Components and Technology Conference (ECTC), 2009, pp. 1289-1296.
[14] G. Pares, C. Bouvier, M. Saadaoui, J. Mazuir, J. Noiray, K. Martinschitz, A. Planchais, and G. Simon, "3D Embedded Wafer-Level Packagin Technology Development for Smart Card SIP Application", Proc. Electronics Packaging Technology Conference (EPTC), 2012, pp. 304-310.
[15] R. Rajoo, and X. Zhang, "Moisture Characteristics of Wafer Level Compression Molding Compounds", Proc. Electronics Packaging Technology Conference (EPTC), 2011, pp. 147-152.
[16] G. Sharma, A. Kumar, V.S.Rao, S.W. Ho, and V. Kripesh, "Solutions Strategies for Die Shift Problem in Wafer Level Compression Molding", Components, Packaging and Manufacturing Technology (CPMT), 2011, vol. 1 (4), pp. 502-509.
[17] C. Scanlan, B. Rogers, T. Olson, C. Bishop, J. Kellar, and B.Y. Jung, "Adaptive Patterning for Panelized Packaging", Proc. International Wafer Level Packaging Conference (IWLPC), 2012.
[18] R.M. Waxler, and C.E. Weir, "Effect of Pressure and Temperature on the Refractive Indices of Benzene, Carbon Tetrachloride, and Water", Research of the National Bureau of Standards, 1963, vol. 67A, pp. 163-171.
[19] I. Thormahlen, J. Straub, and U. Grigull, "Refractive Index of Water and Its Dependence on Wavelength, Temperature, and Density", Physical and Chemical Reference Data, 1985, vol. 14(4), pp. 933-945.
[20] A.N. Bashkatov, and E.A. Genina, "Water refractive index in dependence on temperature and wavelength: a simple approximation", Proc. SPIE, 2003, vol. 5068, pp393-365.
[21] T. Braun, K.-F. Becker, S. Voges, J. Bauer, R. Kahle, V. Bader, T. Thomas, R. Aschenbrenner, and K.-D. Lang, "24"×18" Fan-out panel level packing", Proc. Electronic Components and Technology Conference (ECTC), 2014, pp. 940-946.
[22] T. Braun, K.-F. Becker, S. Voges, T. Thomas, R. Kahle, V. Bader, J. Bauer, R. Aschenbrenner, and K.-D. Lang, "Challenges and Opportunities for Fan-out Panel Level Packing (FOPLP)", Proc. International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2014, pp.154-157.
[23] S. Owa, K. Nakano, H. Nagasaka, T. Fujiwara, T. Matsuyama, Y. Ohmura, and H. Magoon, "Immersion Lithography Ready for 45 nm Manufacturing and Beyond", Proc. Advanced Semiconductor Manufacturing Conference, 2007, pp. 238-244.
[24] S.R.J. Brueck, "Optical and Interferometric Lithography-Nanotechnology Enablers", Proc. of the IEEE, 2005, vol. 93 (10), pp. 1704-1721.
[25] R.F. Pease, and S.Y. Chou, "Lithography and Other Patterning Techniques for Future Electronics", Proc. IEEE, 2007, vol. 96 (2), pp. 248-270.
[26] S. Owa, and H. Nagasaka "Immersion Lithography: its Potential Performance and Issues", Proc. Optical Microlithography, 2003, vol. 5040, pp. 724-733.
[27] B.J. Lin, "Immersion lithography and its impact on semiconductor manufacturing", Micro/Nanolithography, MEMS, and MOEM, 2004, vol. 3(3), pp. 377-395.
[28] Yole_Nanium Workshop, "Semi Networking Day Packaging – Key for System Integration", YOLE Development, 2013.
 
 
 
 
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