由於單電子電晶體(Single-Electron Transistor)在室溫下的操作過程耗能極低，它有望成為能夠延續摩爾定律的裝置。目前既有的單電子電晶體架構之合成方法是將一個布林網路合成成一個高度和主要輸入(Primary Input)個數相同的可重構單電子電晶體架構，然而，近來裝置方面的實驗顯示出此高度受到極低電流的影響，必須限制在一個數字內，例如10，而非任意數。此外，單電子電晶體架構的寬度也建議被縮減。因此，將一個大的單電子電晶體架構分解成多個高度不超過10的單電子電晶體架構是必要的。本論文提出兩個技術來達到面積有效的單電
子電晶體架構之分解：第一項技術是用於縮減單一一個單電子電晶體架構的寬度最小化演算法；另一項技術是深度綁定的映射演算法，用於將一個布林網路分解成多個寬度平衡的子函數。寬度最小化演算法與最先進的技術相比有25%~41%之進步，而映射演算法與簡易映射演算法相比能省下60%之面積。

Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra-low power consumption.
Existing SET synthesis methods synthesize a Boolean network into a large recongurable SET array where the height of SET array equals the number of primary
inputs. However, recent experiments on device level have shown that this height is restricted to a small number, say 10, rather than arbitrary value due to the ultra-low
driving strength of SET devices. On the other hand, the width of an SET array is also suggested to be a small value. Consequently, it is necessary to decompose a large
SET array into a set of small SET arrays where each of them realizes a sub-function of the original circuit with no more than 10 inputs. Thus, this paper presents two
techniques for achieving area-efficient SET array decomposition: One is a width minimization algorithm for reducing the area of a single SET array; the other is a
depth-bounded mapping algorithm, which decomposes a Boolean network into many sub-functions such that the widths of the corresponding SET arrays are balanced.
The width minimization algorithm leads to a 25%~41% improvement compared to the state-of-the-art, and the mapping algorithm achieves a 60% reduction in total
area compared to a naive approach.

中文摘要i
Abstract ii
Acknowledgement iii
Contents iv
List of Tables vi
List of Figures vii
1 Introduction 1
2 Background 4
2.1 Recongurable SET Array . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Symmetric Fabric Constraint . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Product-term-based SET Array Synthesis . . . . . . . . . . . . . . . . 5
2.4 Branch-then-Share . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5 SET Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 SET Array Width Minimization 7
3.1 BTS Identication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.1 BTS Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.2 Con
icting BTSs Removal . . . . . . . . . . . . . . . . . . . . 9
3.1.3 Exploring Maximal Number of BTS . . . . . . . . . . . . . . . 10
3.2 Synthesis for Width Minimization . . . . . . . . . . . . . . . . . . . . 11
4 Mapping for SET Network 13
4.1 Overview of SET Network Mapping Algorithm . . . . . . . . . . . . . 14
4.2 Cut Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Potential Width Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.1 Potential Width Associated with a Cut . . . . . . . . . . . . . 17
4.3.2 The determination of a Bound of Potential Width . . . . . . . 17
4.4 Depth-bounded Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5 Area Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6 Final Mapping Derivation . . . . . . . . . . . . . . . . . . . . . . . . 20
4.7 Overall Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 Experimental Results 22
5.1 Comparison of Width for SET Arrays without Decomposition . . . . 22
5.1.1 Comparison of BTS Exploration Algorithms . . . . . . . . . . 23
5.1.2 Comparison of Overall SET Array Synthesis Flows . . . . . . 23
5.2 Comparison of Total Area in SET Networks . . . . . . . . . . . . . . 24
6 Conclusion 29

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