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作者(中文):林承毅
作者(外文):Lin, Cheng Yi
論文名稱(中文):藉由個別連接埠快取電路加速 OpenFlow 網路交換器
論文名稱(外文):Accelerating OpenFlow Switches with Per-Port Cache
指導教授(中文):林永隆
指導教授(外文):Lin, Youn-Long
口試委員(中文):黃稚存
黃俊達
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學號:102062501
出版年(民國):104
畢業學年度:103
語文別:英文
論文頁數:41
中文關鍵詞:軟體定義網路快取連接埠交換器加速
外文關鍵詞:SDNsoftware defined networkper-port cacheOpenflow SwitchAccelerating
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本篇論文提出一個供 Openflow 交換器使用的快取設計。我們以硬體來實作交換器的路由並用軟體來實作搜尋引擎。藉由分析國立清華大學計算機通訊中心的網路流量資料,我們觀察到網路封包和交換器的連接埠之間存在空間局部性。我們提出了一個各別連接埠快取的設計來妥善利用此空間局部性。這個設計以Verilog語言和C語言實作的搜尋引擎來實作。我們以不同的快取配置、網路流量和網路拓撲來測試我們的設計原型。和常用的軟體交換器 - Open vSwitch相比,我們的設計可以用相當少的成本來增加交換器的效能。
We propose a cache design for an OpenFlow switch which implements datapath in hardware and search engine in software.
By analyzing some of National Tsing Hua University traffic records from the Computer and Communication Center, we observe that flows and switch ports exhibit spatial locality.
We propose a per-port cache design to take advantage of those spatial locality.
The design is implemented in Verilog together with a C-based search engine.
We evaluate our prototype with various cache configurations, traffic patterns and topologies.
Compared with a popular software Open vSwitch , our per-port cache design improves switch performance with little overhead.
1 Introduction
2 Related Work
3 Per-port Cache of Flow Table
3.1 Per-Port Cache for Capturing Spatial Locality of Network Flows
3.2 Whitebox Switch RTL Design
3.3 Veri cation in co-emulation
4 Performance Evaluation
4.1 Experimental Environment and Measurement
4.2 Limitations
4.3 Result and Analysis
5 Conclusion and Future Work
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